1 // megafunction wizard: %FIFO%CBX%
2 // GENERATION: STANDARD
6 // ============================================================
7 // File Name: fifo_4k.v
8 // Megafunction Name(s):
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
14 // 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
15 // ************************************************************
18 //Copyright (C) 1991-2005 Altera Corporation
19 //Your use of Altera Corporation's design tools, logic functions
20 //and other software and tools, and its AMPP partner logic
21 //functions, and any output files any of the foregoing
22 //(including device programming or simulation files), and any
23 //associated documentation or information are expressly subject
24 //to the terms and conditions of the Altera Program License
25 //Subscription Agreement, Altera MegaCore Function License
26 //Agreement, or other applicable license agreement, including,
27 //without limitation, that your use is for the sole purpose of
28 //programming logic devices manufactured by Altera and sold by
29 //Altera or its authorized distributors. Please refer to the
30 //applicable agreement for further details.
33 //dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
34 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
37 //a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
38 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ VERSION_END
40 //synthesis_resources =
41 //synopsys translate_off
42 `timescale 1 ps / 1 ps
43 //synopsys translate_on
44 module fifo_4k_a_gray2bin_9m4
47 gray) /* synthesis synthesis_clearbox=1 */;
64 bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
65 xor0 = (gray[0] ^ xor1),
66 xor1 = (gray[1] ^ xor2),
67 xor10 = (gray[11] ^ gray[10]),
68 xor2 = (gray[2] ^ xor3),
69 xor3 = (gray[3] ^ xor4),
70 xor4 = (gray[4] ^ xor5),
71 xor5 = (gray[5] ^ xor6),
72 xor6 = (gray[6] ^ xor7),
73 xor7 = (gray[7] ^ xor8),
74 xor8 = (gray[8] ^ xor9),
75 xor9 = (gray[9] ^ xor10);
76 endmodule //fifo_4k_a_gray2bin_9m4
79 //a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
80 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
82 //synthesis_resources = lut 13
83 //synopsys translate_off
84 `timescale 1 ps / 1 ps
85 //synopsys translate_on
86 module fifo_4k_a_graycounter_826
91 q) /* synthesis synthesis_clearbox=1 */;
97 wire [0:0] wire_countera_0cout;
98 wire [0:0] wire_countera_1cout;
99 wire [0:0] wire_countera_2cout;
100 wire [0:0] wire_countera_3cout;
101 wire [0:0] wire_countera_4cout;
102 wire [0:0] wire_countera_5cout;
103 wire [0:0] wire_countera_6cout;
104 wire [0:0] wire_countera_7cout;
105 wire [0:0] wire_countera_8cout;
106 wire [0:0] wire_countera_9cout;
107 wire [0:0] wire_countera_10cout;
108 wire [11:0] wire_countera_regout;
109 wire wire_parity_cout;
110 wire wire_parity_regout;
111 wire [11:0] power_modified_counter_values;
115 cyclone_lcell countera_0
118 .cin(wire_parity_cout),
121 .cout(wire_countera_0cout[0:0]),
123 .datab(wire_countera_regout[0:0]),
125 .regout(wire_countera_regout[0:0]),
127 `ifdef FORMAL_VERIFICATION
129 // synopsys translate_off
138 `ifdef FORMAL_VERIFICATION
140 // synopsys translate_on
142 // synopsys translate_off
150 // synopsys translate_on
153 countera_0.cin_used = "true",
154 countera_0.lut_mask = "c6a0",
155 countera_0.operation_mode = "arithmetic",
156 countera_0.sum_lutc_input = "cin",
157 countera_0.synch_mode = "on",
158 countera_0.lpm_type = "cyclone_lcell";
159 cyclone_lcell countera_1
162 .cin(wire_countera_0cout[0:0]),
165 .cout(wire_countera_1cout[0:0]),
166 .dataa(power_modified_counter_values[0]),
167 .datab(power_modified_counter_values[1]),
169 .regout(wire_countera_regout[1:1]),
171 `ifdef FORMAL_VERIFICATION
173 // synopsys translate_off
182 `ifdef FORMAL_VERIFICATION
184 // synopsys translate_on
186 // synopsys translate_off
194 // synopsys translate_on
197 countera_1.cin_used = "true",
198 countera_1.lut_mask = "6c50",
199 countera_1.operation_mode = "arithmetic",
200 countera_1.sum_lutc_input = "cin",
201 countera_1.synch_mode = "on",
202 countera_1.lpm_type = "cyclone_lcell";
203 cyclone_lcell countera_2
206 .cin(wire_countera_1cout[0:0]),
209 .cout(wire_countera_2cout[0:0]),
210 .dataa(power_modified_counter_values[1]),
211 .datab(power_modified_counter_values[2]),
213 .regout(wire_countera_regout[2:2]),
215 `ifdef FORMAL_VERIFICATION
217 // synopsys translate_off
226 `ifdef FORMAL_VERIFICATION
228 // synopsys translate_on
230 // synopsys translate_off
238 // synopsys translate_on
241 countera_2.cin_used = "true",
242 countera_2.lut_mask = "6c50",
243 countera_2.operation_mode = "arithmetic",
244 countera_2.sum_lutc_input = "cin",
245 countera_2.synch_mode = "on",
246 countera_2.lpm_type = "cyclone_lcell";
247 cyclone_lcell countera_3
250 .cin(wire_countera_2cout[0:0]),
253 .cout(wire_countera_3cout[0:0]),
254 .dataa(power_modified_counter_values[2]),
255 .datab(power_modified_counter_values[3]),
257 .regout(wire_countera_regout[3:3]),
259 `ifdef FORMAL_VERIFICATION
261 // synopsys translate_off
270 `ifdef FORMAL_VERIFICATION
272 // synopsys translate_on
274 // synopsys translate_off
282 // synopsys translate_on
285 countera_3.cin_used = "true",
286 countera_3.lut_mask = "6c50",
287 countera_3.operation_mode = "arithmetic",
288 countera_3.sum_lutc_input = "cin",
289 countera_3.synch_mode = "on",
290 countera_3.lpm_type = "cyclone_lcell";
291 cyclone_lcell countera_4
294 .cin(wire_countera_3cout[0:0]),
297 .cout(wire_countera_4cout[0:0]),
298 .dataa(power_modified_counter_values[3]),
299 .datab(power_modified_counter_values[4]),
301 .regout(wire_countera_regout[4:4]),
303 `ifdef FORMAL_VERIFICATION
305 // synopsys translate_off
314 `ifdef FORMAL_VERIFICATION
316 // synopsys translate_on
318 // synopsys translate_off
326 // synopsys translate_on
329 countera_4.cin_used = "true",
330 countera_4.lut_mask = "6c50",
331 countera_4.operation_mode = "arithmetic",
332 countera_4.sum_lutc_input = "cin",
333 countera_4.synch_mode = "on",
334 countera_4.lpm_type = "cyclone_lcell";
335 cyclone_lcell countera_5
338 .cin(wire_countera_4cout[0:0]),
341 .cout(wire_countera_5cout[0:0]),
342 .dataa(power_modified_counter_values[4]),
343 .datab(power_modified_counter_values[5]),
345 .regout(wire_countera_regout[5:5]),
347 `ifdef FORMAL_VERIFICATION
349 // synopsys translate_off
358 `ifdef FORMAL_VERIFICATION
360 // synopsys translate_on
362 // synopsys translate_off
370 // synopsys translate_on
373 countera_5.cin_used = "true",
374 countera_5.lut_mask = "6c50",
375 countera_5.operation_mode = "arithmetic",
376 countera_5.sum_lutc_input = "cin",
377 countera_5.synch_mode = "on",
378 countera_5.lpm_type = "cyclone_lcell";
379 cyclone_lcell countera_6
382 .cin(wire_countera_5cout[0:0]),
385 .cout(wire_countera_6cout[0:0]),
386 .dataa(power_modified_counter_values[5]),
387 .datab(power_modified_counter_values[6]),
389 .regout(wire_countera_regout[6:6]),
391 `ifdef FORMAL_VERIFICATION
393 // synopsys translate_off
402 `ifdef FORMAL_VERIFICATION
404 // synopsys translate_on
406 // synopsys translate_off
414 // synopsys translate_on
417 countera_6.cin_used = "true",
418 countera_6.lut_mask = "6c50",
419 countera_6.operation_mode = "arithmetic",
420 countera_6.sum_lutc_input = "cin",
421 countera_6.synch_mode = "on",
422 countera_6.lpm_type = "cyclone_lcell";
423 cyclone_lcell countera_7
426 .cin(wire_countera_6cout[0:0]),
429 .cout(wire_countera_7cout[0:0]),
430 .dataa(power_modified_counter_values[6]),
431 .datab(power_modified_counter_values[7]),
433 .regout(wire_countera_regout[7:7]),
435 `ifdef FORMAL_VERIFICATION
437 // synopsys translate_off
446 `ifdef FORMAL_VERIFICATION
448 // synopsys translate_on
450 // synopsys translate_off
458 // synopsys translate_on
461 countera_7.cin_used = "true",
462 countera_7.lut_mask = "6c50",
463 countera_7.operation_mode = "arithmetic",
464 countera_7.sum_lutc_input = "cin",
465 countera_7.synch_mode = "on",
466 countera_7.lpm_type = "cyclone_lcell";
467 cyclone_lcell countera_8
470 .cin(wire_countera_7cout[0:0]),
473 .cout(wire_countera_8cout[0:0]),
474 .dataa(power_modified_counter_values[7]),
475 .datab(power_modified_counter_values[8]),
477 .regout(wire_countera_regout[8:8]),
479 `ifdef FORMAL_VERIFICATION
481 // synopsys translate_off
490 `ifdef FORMAL_VERIFICATION
492 // synopsys translate_on
494 // synopsys translate_off
502 // synopsys translate_on
505 countera_8.cin_used = "true",
506 countera_8.lut_mask = "6c50",
507 countera_8.operation_mode = "arithmetic",
508 countera_8.sum_lutc_input = "cin",
509 countera_8.synch_mode = "on",
510 countera_8.lpm_type = "cyclone_lcell";
511 cyclone_lcell countera_9
514 .cin(wire_countera_8cout[0:0]),
517 .cout(wire_countera_9cout[0:0]),
518 .dataa(power_modified_counter_values[8]),
519 .datab(power_modified_counter_values[9]),
521 .regout(wire_countera_regout[9:9]),
523 `ifdef FORMAL_VERIFICATION
525 // synopsys translate_off
534 `ifdef FORMAL_VERIFICATION
536 // synopsys translate_on
538 // synopsys translate_off
546 // synopsys translate_on
549 countera_9.cin_used = "true",
550 countera_9.lut_mask = "6c50",
551 countera_9.operation_mode = "arithmetic",
552 countera_9.sum_lutc_input = "cin",
553 countera_9.synch_mode = "on",
554 countera_9.lpm_type = "cyclone_lcell";
555 cyclone_lcell countera_10
558 .cin(wire_countera_9cout[0:0]),
561 .cout(wire_countera_10cout[0:0]),
562 .dataa(power_modified_counter_values[9]),
563 .datab(power_modified_counter_values[10]),
565 .regout(wire_countera_regout[10:10]),
567 `ifdef FORMAL_VERIFICATION
569 // synopsys translate_off
578 `ifdef FORMAL_VERIFICATION
580 // synopsys translate_on
582 // synopsys translate_off
590 // synopsys translate_on
593 countera_10.cin_used = "true",
594 countera_10.lut_mask = "6c50",
595 countera_10.operation_mode = "arithmetic",
596 countera_10.sum_lutc_input = "cin",
597 countera_10.synch_mode = "on",
598 countera_10.lpm_type = "cyclone_lcell";
599 cyclone_lcell countera_11
602 .cin(wire_countera_10cout[0:0]),
606 .dataa(power_modified_counter_values[11]),
608 .regout(wire_countera_regout[11:11]),
610 `ifdef FORMAL_VERIFICATION
612 // synopsys translate_off
622 `ifdef FORMAL_VERIFICATION
624 // synopsys translate_on
626 // synopsys translate_off
634 // synopsys translate_on
637 countera_11.cin_used = "true",
638 countera_11.lut_mask = "5a5a",
639 countera_11.operation_mode = "normal",
640 countera_11.sum_lutc_input = "cin",
641 countera_11.synch_mode = "on",
642 countera_11.lpm_type = "cyclone_lcell";
649 .cout(wire_parity_cout),
651 .datab(wire_parity_regout),
653 .regout(wire_parity_regout),
655 `ifdef FORMAL_VERIFICATION
657 // synopsys translate_off
666 `ifdef FORMAL_VERIFICATION
668 // synopsys translate_on
670 // synopsys translate_off
678 // synopsys translate_on
681 parity.cin_used = "true",
682 parity.lut_mask = "6682",
683 parity.operation_mode = "arithmetic",
684 parity.synch_mode = "on",
685 parity.lpm_type = "cyclone_lcell";
687 power_modified_counter_values = {wire_countera_regout[11:0]},
688 q = power_modified_counter_values,
691 endmodule //fifo_4k_a_graycounter_826
694 //a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
695 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
697 //synthesis_resources = lut 13
698 //synopsys translate_off
699 `timescale 1 ps / 1 ps
700 //synopsys translate_on
701 module fifo_4k_a_graycounter_3r6
706 q) /* synthesis synthesis_clearbox=1 */;
712 wire [0:0] wire_countera_0cout;
713 wire [0:0] wire_countera_1cout;
714 wire [0:0] wire_countera_2cout;
715 wire [0:0] wire_countera_3cout;
716 wire [0:0] wire_countera_4cout;
717 wire [0:0] wire_countera_5cout;
718 wire [0:0] wire_countera_6cout;
719 wire [0:0] wire_countera_7cout;
720 wire [0:0] wire_countera_8cout;
721 wire [0:0] wire_countera_9cout;
722 wire [0:0] wire_countera_10cout;
723 wire [11:0] wire_countera_regout;
724 wire wire_parity_cout;
725 wire wire_parity_regout;
726 wire [11:0] power_modified_counter_values;
730 cyclone_lcell countera_0
733 .cin(wire_parity_cout),
736 .cout(wire_countera_0cout[0:0]),
738 .datab(wire_countera_regout[0:0]),
740 .regout(wire_countera_regout[0:0]),
742 `ifdef FORMAL_VERIFICATION
744 // synopsys translate_off
753 `ifdef FORMAL_VERIFICATION
755 // synopsys translate_on
757 // synopsys translate_off
765 // synopsys translate_on
768 countera_0.cin_used = "true",
769 countera_0.lut_mask = "c6a0",
770 countera_0.operation_mode = "arithmetic",
771 countera_0.sum_lutc_input = "cin",
772 countera_0.synch_mode = "on",
773 countera_0.lpm_type = "cyclone_lcell";
774 cyclone_lcell countera_1
777 .cin(wire_countera_0cout[0:0]),
780 .cout(wire_countera_1cout[0:0]),
781 .dataa(power_modified_counter_values[0]),
782 .datab(power_modified_counter_values[1]),
784 .regout(wire_countera_regout[1:1]),
786 `ifdef FORMAL_VERIFICATION
788 // synopsys translate_off
797 `ifdef FORMAL_VERIFICATION
799 // synopsys translate_on
801 // synopsys translate_off
809 // synopsys translate_on
812 countera_1.cin_used = "true",
813 countera_1.lut_mask = "6c50",
814 countera_1.operation_mode = "arithmetic",
815 countera_1.sum_lutc_input = "cin",
816 countera_1.synch_mode = "on",
817 countera_1.lpm_type = "cyclone_lcell";
818 cyclone_lcell countera_2
821 .cin(wire_countera_1cout[0:0]),
824 .cout(wire_countera_2cout[0:0]),
825 .dataa(power_modified_counter_values[1]),
826 .datab(power_modified_counter_values[2]),
828 .regout(wire_countera_regout[2:2]),
830 `ifdef FORMAL_VERIFICATION
832 // synopsys translate_off
841 `ifdef FORMAL_VERIFICATION
843 // synopsys translate_on
845 // synopsys translate_off
853 // synopsys translate_on
856 countera_2.cin_used = "true",
857 countera_2.lut_mask = "6c50",
858 countera_2.operation_mode = "arithmetic",
859 countera_2.sum_lutc_input = "cin",
860 countera_2.synch_mode = "on",
861 countera_2.lpm_type = "cyclone_lcell";
862 cyclone_lcell countera_3
865 .cin(wire_countera_2cout[0:0]),
868 .cout(wire_countera_3cout[0:0]),
869 .dataa(power_modified_counter_values[2]),
870 .datab(power_modified_counter_values[3]),
872 .regout(wire_countera_regout[3:3]),
874 `ifdef FORMAL_VERIFICATION
876 // synopsys translate_off
885 `ifdef FORMAL_VERIFICATION
887 // synopsys translate_on
889 // synopsys translate_off
897 // synopsys translate_on
900 countera_3.cin_used = "true",
901 countera_3.lut_mask = "6c50",
902 countera_3.operation_mode = "arithmetic",
903 countera_3.sum_lutc_input = "cin",
904 countera_3.synch_mode = "on",
905 countera_3.lpm_type = "cyclone_lcell";
906 cyclone_lcell countera_4
909 .cin(wire_countera_3cout[0:0]),
912 .cout(wire_countera_4cout[0:0]),
913 .dataa(power_modified_counter_values[3]),
914 .datab(power_modified_counter_values[4]),
916 .regout(wire_countera_regout[4:4]),
918 `ifdef FORMAL_VERIFICATION
920 // synopsys translate_off
929 `ifdef FORMAL_VERIFICATION
931 // synopsys translate_on
933 // synopsys translate_off
941 // synopsys translate_on
944 countera_4.cin_used = "true",
945 countera_4.lut_mask = "6c50",
946 countera_4.operation_mode = "arithmetic",
947 countera_4.sum_lutc_input = "cin",
948 countera_4.synch_mode = "on",
949 countera_4.lpm_type = "cyclone_lcell";
950 cyclone_lcell countera_5
953 .cin(wire_countera_4cout[0:0]),
956 .cout(wire_countera_5cout[0:0]),
957 .dataa(power_modified_counter_values[4]),
958 .datab(power_modified_counter_values[5]),
960 .regout(wire_countera_regout[5:5]),
962 `ifdef FORMAL_VERIFICATION
964 // synopsys translate_off
973 `ifdef FORMAL_VERIFICATION
975 // synopsys translate_on
977 // synopsys translate_off
985 // synopsys translate_on
988 countera_5.cin_used = "true",
989 countera_5.lut_mask = "6c50",
990 countera_5.operation_mode = "arithmetic",
991 countera_5.sum_lutc_input = "cin",
992 countera_5.synch_mode = "on",
993 countera_5.lpm_type = "cyclone_lcell";
994 cyclone_lcell countera_6
997 .cin(wire_countera_5cout[0:0]),
1000 .cout(wire_countera_6cout[0:0]),
1001 .dataa(power_modified_counter_values[5]),
1002 .datab(power_modified_counter_values[6]),
1004 .regout(wire_countera_regout[6:6]),
1006 `ifdef FORMAL_VERIFICATION
1008 // synopsys translate_off
1017 `ifdef FORMAL_VERIFICATION
1019 // synopsys translate_on
1021 // synopsys translate_off
1029 // synopsys translate_on
1032 countera_6.cin_used = "true",
1033 countera_6.lut_mask = "6c50",
1034 countera_6.operation_mode = "arithmetic",
1035 countera_6.sum_lutc_input = "cin",
1036 countera_6.synch_mode = "on",
1037 countera_6.lpm_type = "cyclone_lcell";
1038 cyclone_lcell countera_7
1041 .cin(wire_countera_6cout[0:0]),
1044 .cout(wire_countera_7cout[0:0]),
1045 .dataa(power_modified_counter_values[6]),
1046 .datab(power_modified_counter_values[7]),
1048 .regout(wire_countera_regout[7:7]),
1050 `ifdef FORMAL_VERIFICATION
1052 // synopsys translate_off
1061 `ifdef FORMAL_VERIFICATION
1063 // synopsys translate_on
1065 // synopsys translate_off
1073 // synopsys translate_on
1076 countera_7.cin_used = "true",
1077 countera_7.lut_mask = "6c50",
1078 countera_7.operation_mode = "arithmetic",
1079 countera_7.sum_lutc_input = "cin",
1080 countera_7.synch_mode = "on",
1081 countera_7.lpm_type = "cyclone_lcell";
1082 cyclone_lcell countera_8
1085 .cin(wire_countera_7cout[0:0]),
1088 .cout(wire_countera_8cout[0:0]),
1089 .dataa(power_modified_counter_values[7]),
1090 .datab(power_modified_counter_values[8]),
1092 .regout(wire_countera_regout[8:8]),
1094 `ifdef FORMAL_VERIFICATION
1096 // synopsys translate_off
1105 `ifdef FORMAL_VERIFICATION
1107 // synopsys translate_on
1109 // synopsys translate_off
1117 // synopsys translate_on
1120 countera_8.cin_used = "true",
1121 countera_8.lut_mask = "6c50",
1122 countera_8.operation_mode = "arithmetic",
1123 countera_8.sum_lutc_input = "cin",
1124 countera_8.synch_mode = "on",
1125 countera_8.lpm_type = "cyclone_lcell";
1126 cyclone_lcell countera_9
1129 .cin(wire_countera_8cout[0:0]),
1132 .cout(wire_countera_9cout[0:0]),
1133 .dataa(power_modified_counter_values[8]),
1134 .datab(power_modified_counter_values[9]),
1136 .regout(wire_countera_regout[9:9]),
1138 `ifdef FORMAL_VERIFICATION
1140 // synopsys translate_off
1149 `ifdef FORMAL_VERIFICATION
1151 // synopsys translate_on
1153 // synopsys translate_off
1161 // synopsys translate_on
1164 countera_9.cin_used = "true",
1165 countera_9.lut_mask = "6c50",
1166 countera_9.operation_mode = "arithmetic",
1167 countera_9.sum_lutc_input = "cin",
1168 countera_9.synch_mode = "on",
1169 countera_9.lpm_type = "cyclone_lcell";
1170 cyclone_lcell countera_10
1173 .cin(wire_countera_9cout[0:0]),
1176 .cout(wire_countera_10cout[0:0]),
1177 .dataa(power_modified_counter_values[9]),
1178 .datab(power_modified_counter_values[10]),
1180 .regout(wire_countera_regout[10:10]),
1182 `ifdef FORMAL_VERIFICATION
1184 // synopsys translate_off
1193 `ifdef FORMAL_VERIFICATION
1195 // synopsys translate_on
1197 // synopsys translate_off
1205 // synopsys translate_on
1208 countera_10.cin_used = "true",
1209 countera_10.lut_mask = "6c50",
1210 countera_10.operation_mode = "arithmetic",
1211 countera_10.sum_lutc_input = "cin",
1212 countera_10.synch_mode = "on",
1213 countera_10.lpm_type = "cyclone_lcell";
1214 cyclone_lcell countera_11
1217 .cin(wire_countera_10cout[0:0]),
1221 .dataa(power_modified_counter_values[11]),
1223 .regout(wire_countera_regout[11:11]),
1225 `ifdef FORMAL_VERIFICATION
1227 // synopsys translate_off
1237 `ifdef FORMAL_VERIFICATION
1239 // synopsys translate_on
1241 // synopsys translate_off
1249 // synopsys translate_on
1252 countera_11.cin_used = "true",
1253 countera_11.lut_mask = "5a5a",
1254 countera_11.operation_mode = "normal",
1255 countera_11.sum_lutc_input = "cin",
1256 countera_11.synch_mode = "on",
1257 countera_11.lpm_type = "cyclone_lcell";
1258 cyclone_lcell parity
1264 .cout(wire_parity_cout),
1266 .datab((~ wire_parity_regout)),
1268 .regout(wire_parity_regout),
1270 `ifdef FORMAL_VERIFICATION
1272 // synopsys translate_off
1281 `ifdef FORMAL_VERIFICATION
1283 // synopsys translate_on
1285 // synopsys translate_off
1293 // synopsys translate_on
1296 parity.cin_used = "true",
1297 parity.lut_mask = "9982",
1298 parity.operation_mode = "arithmetic",
1299 parity.synch_mode = "on",
1300 parity.lpm_type = "cyclone_lcell";
1302 power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
1303 q = power_modified_counter_values,
1306 endmodule //fifo_4k_a_graycounter_3r6
1309 //altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
1310 //VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
1312 //synthesis_resources = M4K 16
1313 //synopsys translate_off
1314 `timescale 1 ps / 1 ps
1315 //synopsys translate_on
1316 module fifo_4k_altsyncram_8pl
1325 wren_a) /* synthesis synthesis_clearbox=1 */;
1326 input [11:0] address_a;
1327 input [11:0] address_b;
1331 input [15:0] data_a;
1335 wire [0:0] wire_ram_block3a_0portbdataout;
1336 wire [0:0] wire_ram_block3a_1portbdataout;
1337 wire [0:0] wire_ram_block3a_2portbdataout;
1338 wire [0:0] wire_ram_block3a_3portbdataout;
1339 wire [0:0] wire_ram_block3a_4portbdataout;
1340 wire [0:0] wire_ram_block3a_5portbdataout;
1341 wire [0:0] wire_ram_block3a_6portbdataout;
1342 wire [0:0] wire_ram_block3a_7portbdataout;
1343 wire [0:0] wire_ram_block3a_8portbdataout;
1344 wire [0:0] wire_ram_block3a_9portbdataout;
1345 wire [0:0] wire_ram_block3a_10portbdataout;
1346 wire [0:0] wire_ram_block3a_11portbdataout;
1347 wire [0:0] wire_ram_block3a_12portbdataout;
1348 wire [0:0] wire_ram_block3a_13portbdataout;
1349 wire [0:0] wire_ram_block3a_14portbdataout;
1350 wire [0:0] wire_ram_block3a_15portbdataout;
1351 wire [11:0] address_a_wire;
1352 wire [11:0] address_b_wire;
1354 cyclone_ram_block ram_block3a_0
1360 .portaaddr({address_a_wire[11:0]}),
1361 .portadatain({data_a[0]}),
1364 .portbaddr({address_b_wire[11:0]}),
1365 .portbdataout(wire_ram_block3a_0portbdataout[0:0]),
1367 `ifdef FORMAL_VERIFICATION
1369 // synopsys translate_off
1374 .portabyteenamasks(1'b1),
1375 .portbbyteenamasks(1'b1),
1377 `ifdef FORMAL_VERIFICATION
1379 // synopsys translate_on
1381 // synopsys translate_off
1385 // synopsys translate_on
1388 ram_block3a_0.connectivity_checking = "OFF",
1389 ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
1390 ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
1391 ram_block3a_0.operation_mode = "dual_port",
1392 ram_block3a_0.port_a_address_width = 12,
1393 ram_block3a_0.port_a_data_width = 1,
1394 ram_block3a_0.port_a_first_address = 0,
1395 ram_block3a_0.port_a_first_bit_number = 0,
1396 ram_block3a_0.port_a_last_address = 4095,
1397 ram_block3a_0.port_a_logical_ram_depth = 4096,
1398 ram_block3a_0.port_a_logical_ram_width = 16,
1399 ram_block3a_0.port_b_address_clear = "none",
1400 ram_block3a_0.port_b_address_clock = "clock1",
1401 ram_block3a_0.port_b_address_width = 12,
1402 ram_block3a_0.port_b_data_out_clear = "none",
1403 ram_block3a_0.port_b_data_out_clock = "none",
1404 ram_block3a_0.port_b_data_width = 1,
1405 ram_block3a_0.port_b_first_address = 0,
1406 ram_block3a_0.port_b_first_bit_number = 0,
1407 ram_block3a_0.port_b_last_address = 4095,
1408 ram_block3a_0.port_b_logical_ram_depth = 4096,
1409 ram_block3a_0.port_b_logical_ram_width = 16,
1410 ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
1411 ram_block3a_0.ram_block_type = "auto",
1412 ram_block3a_0.lpm_type = "cyclone_ram_block";
1413 cyclone_ram_block ram_block3a_1
1419 .portaaddr({address_a_wire[11:0]}),
1420 .portadatain({data_a[1]}),
1423 .portbaddr({address_b_wire[11:0]}),
1424 .portbdataout(wire_ram_block3a_1portbdataout[0:0]),
1426 `ifdef FORMAL_VERIFICATION
1428 // synopsys translate_off
1433 .portabyteenamasks(1'b1),
1434 .portbbyteenamasks(1'b1),
1436 `ifdef FORMAL_VERIFICATION
1438 // synopsys translate_on
1440 // synopsys translate_off
1444 // synopsys translate_on
1447 ram_block3a_1.connectivity_checking = "OFF",
1448 ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
1449 ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
1450 ram_block3a_1.operation_mode = "dual_port",
1451 ram_block3a_1.port_a_address_width = 12,
1452 ram_block3a_1.port_a_data_width = 1,
1453 ram_block3a_1.port_a_first_address = 0,
1454 ram_block3a_1.port_a_first_bit_number = 1,
1455 ram_block3a_1.port_a_last_address = 4095,
1456 ram_block3a_1.port_a_logical_ram_depth = 4096,
1457 ram_block3a_1.port_a_logical_ram_width = 16,
1458 ram_block3a_1.port_b_address_clear = "none",
1459 ram_block3a_1.port_b_address_clock = "clock1",
1460 ram_block3a_1.port_b_address_width = 12,
1461 ram_block3a_1.port_b_data_out_clear = "none",
1462 ram_block3a_1.port_b_data_out_clock = "none",
1463 ram_block3a_1.port_b_data_width = 1,
1464 ram_block3a_1.port_b_first_address = 0,
1465 ram_block3a_1.port_b_first_bit_number = 1,
1466 ram_block3a_1.port_b_last_address = 4095,
1467 ram_block3a_1.port_b_logical_ram_depth = 4096,
1468 ram_block3a_1.port_b_logical_ram_width = 16,
1469 ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
1470 ram_block3a_1.ram_block_type = "auto",
1471 ram_block3a_1.lpm_type = "cyclone_ram_block";
1472 cyclone_ram_block ram_block3a_2
1478 .portaaddr({address_a_wire[11:0]}),
1479 .portadatain({data_a[2]}),
1482 .portbaddr({address_b_wire[11:0]}),
1483 .portbdataout(wire_ram_block3a_2portbdataout[0:0]),
1485 `ifdef FORMAL_VERIFICATION
1487 // synopsys translate_off
1492 .portabyteenamasks(1'b1),
1493 .portbbyteenamasks(1'b1),
1495 `ifdef FORMAL_VERIFICATION
1497 // synopsys translate_on
1499 // synopsys translate_off
1503 // synopsys translate_on
1506 ram_block3a_2.connectivity_checking = "OFF",
1507 ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
1508 ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
1509 ram_block3a_2.operation_mode = "dual_port",
1510 ram_block3a_2.port_a_address_width = 12,
1511 ram_block3a_2.port_a_data_width = 1,
1512 ram_block3a_2.port_a_first_address = 0,
1513 ram_block3a_2.port_a_first_bit_number = 2,
1514 ram_block3a_2.port_a_last_address = 4095,
1515 ram_block3a_2.port_a_logical_ram_depth = 4096,
1516 ram_block3a_2.port_a_logical_ram_width = 16,
1517 ram_block3a_2.port_b_address_clear = "none",
1518 ram_block3a_2.port_b_address_clock = "clock1",
1519 ram_block3a_2.port_b_address_width = 12,
1520 ram_block3a_2.port_b_data_out_clear = "none",
1521 ram_block3a_2.port_b_data_out_clock = "none",
1522 ram_block3a_2.port_b_data_width = 1,
1523 ram_block3a_2.port_b_first_address = 0,
1524 ram_block3a_2.port_b_first_bit_number = 2,
1525 ram_block3a_2.port_b_last_address = 4095,
1526 ram_block3a_2.port_b_logical_ram_depth = 4096,
1527 ram_block3a_2.port_b_logical_ram_width = 16,
1528 ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
1529 ram_block3a_2.ram_block_type = "auto",
1530 ram_block3a_2.lpm_type = "cyclone_ram_block";
1531 cyclone_ram_block ram_block3a_3
1537 .portaaddr({address_a_wire[11:0]}),
1538 .portadatain({data_a[3]}),
1541 .portbaddr({address_b_wire[11:0]}),
1542 .portbdataout(wire_ram_block3a_3portbdataout[0:0]),
1544 `ifdef FORMAL_VERIFICATION
1546 // synopsys translate_off
1551 .portabyteenamasks(1'b1),
1552 .portbbyteenamasks(1'b1),
1554 `ifdef FORMAL_VERIFICATION
1556 // synopsys translate_on
1558 // synopsys translate_off
1562 // synopsys translate_on
1565 ram_block3a_3.connectivity_checking = "OFF",
1566 ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
1567 ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
1568 ram_block3a_3.operation_mode = "dual_port",
1569 ram_block3a_3.port_a_address_width = 12,
1570 ram_block3a_3.port_a_data_width = 1,
1571 ram_block3a_3.port_a_first_address = 0,
1572 ram_block3a_3.port_a_first_bit_number = 3,
1573 ram_block3a_3.port_a_last_address = 4095,
1574 ram_block3a_3.port_a_logical_ram_depth = 4096,
1575 ram_block3a_3.port_a_logical_ram_width = 16,
1576 ram_block3a_3.port_b_address_clear = "none",
1577 ram_block3a_3.port_b_address_clock = "clock1",
1578 ram_block3a_3.port_b_address_width = 12,
1579 ram_block3a_3.port_b_data_out_clear = "none",
1580 ram_block3a_3.port_b_data_out_clock = "none",
1581 ram_block3a_3.port_b_data_width = 1,
1582 ram_block3a_3.port_b_first_address = 0,
1583 ram_block3a_3.port_b_first_bit_number = 3,
1584 ram_block3a_3.port_b_last_address = 4095,
1585 ram_block3a_3.port_b_logical_ram_depth = 4096,
1586 ram_block3a_3.port_b_logical_ram_width = 16,
1587 ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
1588 ram_block3a_3.ram_block_type = "auto",
1589 ram_block3a_3.lpm_type = "cyclone_ram_block";
1590 cyclone_ram_block ram_block3a_4
1596 .portaaddr({address_a_wire[11:0]}),
1597 .portadatain({data_a[4]}),
1600 .portbaddr({address_b_wire[11:0]}),
1601 .portbdataout(wire_ram_block3a_4portbdataout[0:0]),
1603 `ifdef FORMAL_VERIFICATION
1605 // synopsys translate_off
1610 .portabyteenamasks(1'b1),
1611 .portbbyteenamasks(1'b1),
1613 `ifdef FORMAL_VERIFICATION
1615 // synopsys translate_on
1617 // synopsys translate_off
1621 // synopsys translate_on
1624 ram_block3a_4.connectivity_checking = "OFF",
1625 ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
1626 ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
1627 ram_block3a_4.operation_mode = "dual_port",
1628 ram_block3a_4.port_a_address_width = 12,
1629 ram_block3a_4.port_a_data_width = 1,
1630 ram_block3a_4.port_a_first_address = 0,
1631 ram_block3a_4.port_a_first_bit_number = 4,
1632 ram_block3a_4.port_a_last_address = 4095,
1633 ram_block3a_4.port_a_logical_ram_depth = 4096,
1634 ram_block3a_4.port_a_logical_ram_width = 16,
1635 ram_block3a_4.port_b_address_clear = "none",
1636 ram_block3a_4.port_b_address_clock = "clock1",
1637 ram_block3a_4.port_b_address_width = 12,
1638 ram_block3a_4.port_b_data_out_clear = "none",
1639 ram_block3a_4.port_b_data_out_clock = "none",
1640 ram_block3a_4.port_b_data_width = 1,
1641 ram_block3a_4.port_b_first_address = 0,
1642 ram_block3a_4.port_b_first_bit_number = 4,
1643 ram_block3a_4.port_b_last_address = 4095,
1644 ram_block3a_4.port_b_logical_ram_depth = 4096,
1645 ram_block3a_4.port_b_logical_ram_width = 16,
1646 ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
1647 ram_block3a_4.ram_block_type = "auto",
1648 ram_block3a_4.lpm_type = "cyclone_ram_block";
1649 cyclone_ram_block ram_block3a_5
1655 .portaaddr({address_a_wire[11:0]}),
1656 .portadatain({data_a[5]}),
1659 .portbaddr({address_b_wire[11:0]}),
1660 .portbdataout(wire_ram_block3a_5portbdataout[0:0]),
1662 `ifdef FORMAL_VERIFICATION
1664 // synopsys translate_off
1669 .portabyteenamasks(1'b1),
1670 .portbbyteenamasks(1'b1),
1672 `ifdef FORMAL_VERIFICATION
1674 // synopsys translate_on
1676 // synopsys translate_off
1680 // synopsys translate_on
1683 ram_block3a_5.connectivity_checking = "OFF",
1684 ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
1685 ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
1686 ram_block3a_5.operation_mode = "dual_port",
1687 ram_block3a_5.port_a_address_width = 12,
1688 ram_block3a_5.port_a_data_width = 1,
1689 ram_block3a_5.port_a_first_address = 0,
1690 ram_block3a_5.port_a_first_bit_number = 5,
1691 ram_block3a_5.port_a_last_address = 4095,
1692 ram_block3a_5.port_a_logical_ram_depth = 4096,
1693 ram_block3a_5.port_a_logical_ram_width = 16,
1694 ram_block3a_5.port_b_address_clear = "none",
1695 ram_block3a_5.port_b_address_clock = "clock1",
1696 ram_block3a_5.port_b_address_width = 12,
1697 ram_block3a_5.port_b_data_out_clear = "none",
1698 ram_block3a_5.port_b_data_out_clock = "none",
1699 ram_block3a_5.port_b_data_width = 1,
1700 ram_block3a_5.port_b_first_address = 0,
1701 ram_block3a_5.port_b_first_bit_number = 5,
1702 ram_block3a_5.port_b_last_address = 4095,
1703 ram_block3a_5.port_b_logical_ram_depth = 4096,
1704 ram_block3a_5.port_b_logical_ram_width = 16,
1705 ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
1706 ram_block3a_5.ram_block_type = "auto",
1707 ram_block3a_5.lpm_type = "cyclone_ram_block";
1708 cyclone_ram_block ram_block3a_6
1714 .portaaddr({address_a_wire[11:0]}),
1715 .portadatain({data_a[6]}),
1718 .portbaddr({address_b_wire[11:0]}),
1719 .portbdataout(wire_ram_block3a_6portbdataout[0:0]),
1721 `ifdef FORMAL_VERIFICATION
1723 // synopsys translate_off
1728 .portabyteenamasks(1'b1),
1729 .portbbyteenamasks(1'b1),
1731 `ifdef FORMAL_VERIFICATION
1733 // synopsys translate_on
1735 // synopsys translate_off
1739 // synopsys translate_on
1742 ram_block3a_6.connectivity_checking = "OFF",
1743 ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
1744 ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
1745 ram_block3a_6.operation_mode = "dual_port",
1746 ram_block3a_6.port_a_address_width = 12,
1747 ram_block3a_6.port_a_data_width = 1,
1748 ram_block3a_6.port_a_first_address = 0,
1749 ram_block3a_6.port_a_first_bit_number = 6,
1750 ram_block3a_6.port_a_last_address = 4095,
1751 ram_block3a_6.port_a_logical_ram_depth = 4096,
1752 ram_block3a_6.port_a_logical_ram_width = 16,
1753 ram_block3a_6.port_b_address_clear = "none",
1754 ram_block3a_6.port_b_address_clock = "clock1",
1755 ram_block3a_6.port_b_address_width = 12,
1756 ram_block3a_6.port_b_data_out_clear = "none",
1757 ram_block3a_6.port_b_data_out_clock = "none",
1758 ram_block3a_6.port_b_data_width = 1,
1759 ram_block3a_6.port_b_first_address = 0,
1760 ram_block3a_6.port_b_first_bit_number = 6,
1761 ram_block3a_6.port_b_last_address = 4095,
1762 ram_block3a_6.port_b_logical_ram_depth = 4096,
1763 ram_block3a_6.port_b_logical_ram_width = 16,
1764 ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
1765 ram_block3a_6.ram_block_type = "auto",
1766 ram_block3a_6.lpm_type = "cyclone_ram_block";
1767 cyclone_ram_block ram_block3a_7
1773 .portaaddr({address_a_wire[11:0]}),
1774 .portadatain({data_a[7]}),
1777 .portbaddr({address_b_wire[11:0]}),
1778 .portbdataout(wire_ram_block3a_7portbdataout[0:0]),
1780 `ifdef FORMAL_VERIFICATION
1782 // synopsys translate_off
1787 .portabyteenamasks(1'b1),
1788 .portbbyteenamasks(1'b1),
1790 `ifdef FORMAL_VERIFICATION
1792 // synopsys translate_on
1794 // synopsys translate_off
1798 // synopsys translate_on
1801 ram_block3a_7.connectivity_checking = "OFF",
1802 ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
1803 ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
1804 ram_block3a_7.operation_mode = "dual_port",
1805 ram_block3a_7.port_a_address_width = 12,
1806 ram_block3a_7.port_a_data_width = 1,
1807 ram_block3a_7.port_a_first_address = 0,
1808 ram_block3a_7.port_a_first_bit_number = 7,
1809 ram_block3a_7.port_a_last_address = 4095,
1810 ram_block3a_7.port_a_logical_ram_depth = 4096,
1811 ram_block3a_7.port_a_logical_ram_width = 16,
1812 ram_block3a_7.port_b_address_clear = "none",
1813 ram_block3a_7.port_b_address_clock = "clock1",
1814 ram_block3a_7.port_b_address_width = 12,
1815 ram_block3a_7.port_b_data_out_clear = "none",
1816 ram_block3a_7.port_b_data_out_clock = "none",
1817 ram_block3a_7.port_b_data_width = 1,
1818 ram_block3a_7.port_b_first_address = 0,
1819 ram_block3a_7.port_b_first_bit_number = 7,
1820 ram_block3a_7.port_b_last_address = 4095,
1821 ram_block3a_7.port_b_logical_ram_depth = 4096,
1822 ram_block3a_7.port_b_logical_ram_width = 16,
1823 ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
1824 ram_block3a_7.ram_block_type = "auto",
1825 ram_block3a_7.lpm_type = "cyclone_ram_block";
1826 cyclone_ram_block ram_block3a_8
1832 .portaaddr({address_a_wire[11:0]}),
1833 .portadatain({data_a[8]}),
1836 .portbaddr({address_b_wire[11:0]}),
1837 .portbdataout(wire_ram_block3a_8portbdataout[0:0]),
1839 `ifdef FORMAL_VERIFICATION
1841 // synopsys translate_off
1846 .portabyteenamasks(1'b1),
1847 .portbbyteenamasks(1'b1),
1849 `ifdef FORMAL_VERIFICATION
1851 // synopsys translate_on
1853 // synopsys translate_off
1857 // synopsys translate_on
1860 ram_block3a_8.connectivity_checking = "OFF",
1861 ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
1862 ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
1863 ram_block3a_8.operation_mode = "dual_port",
1864 ram_block3a_8.port_a_address_width = 12,
1865 ram_block3a_8.port_a_data_width = 1,
1866 ram_block3a_8.port_a_first_address = 0,
1867 ram_block3a_8.port_a_first_bit_number = 8,
1868 ram_block3a_8.port_a_last_address = 4095,
1869 ram_block3a_8.port_a_logical_ram_depth = 4096,
1870 ram_block3a_8.port_a_logical_ram_width = 16,
1871 ram_block3a_8.port_b_address_clear = "none",
1872 ram_block3a_8.port_b_address_clock = "clock1",
1873 ram_block3a_8.port_b_address_width = 12,
1874 ram_block3a_8.port_b_data_out_clear = "none",
1875 ram_block3a_8.port_b_data_out_clock = "none",
1876 ram_block3a_8.port_b_data_width = 1,
1877 ram_block3a_8.port_b_first_address = 0,
1878 ram_block3a_8.port_b_first_bit_number = 8,
1879 ram_block3a_8.port_b_last_address = 4095,
1880 ram_block3a_8.port_b_logical_ram_depth = 4096,
1881 ram_block3a_8.port_b_logical_ram_width = 16,
1882 ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
1883 ram_block3a_8.ram_block_type = "auto",
1884 ram_block3a_8.lpm_type = "cyclone_ram_block";
1885 cyclone_ram_block ram_block3a_9
1891 .portaaddr({address_a_wire[11:0]}),
1892 .portadatain({data_a[9]}),
1895 .portbaddr({address_b_wire[11:0]}),
1896 .portbdataout(wire_ram_block3a_9portbdataout[0:0]),
1898 `ifdef FORMAL_VERIFICATION
1900 // synopsys translate_off
1905 .portabyteenamasks(1'b1),
1906 .portbbyteenamasks(1'b1),
1908 `ifdef FORMAL_VERIFICATION
1910 // synopsys translate_on
1912 // synopsys translate_off
1916 // synopsys translate_on
1919 ram_block3a_9.connectivity_checking = "OFF",
1920 ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
1921 ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
1922 ram_block3a_9.operation_mode = "dual_port",
1923 ram_block3a_9.port_a_address_width = 12,
1924 ram_block3a_9.port_a_data_width = 1,
1925 ram_block3a_9.port_a_first_address = 0,
1926 ram_block3a_9.port_a_first_bit_number = 9,
1927 ram_block3a_9.port_a_last_address = 4095,
1928 ram_block3a_9.port_a_logical_ram_depth = 4096,
1929 ram_block3a_9.port_a_logical_ram_width = 16,
1930 ram_block3a_9.port_b_address_clear = "none",
1931 ram_block3a_9.port_b_address_clock = "clock1",
1932 ram_block3a_9.port_b_address_width = 12,
1933 ram_block3a_9.port_b_data_out_clear = "none",
1934 ram_block3a_9.port_b_data_out_clock = "none",
1935 ram_block3a_9.port_b_data_width = 1,
1936 ram_block3a_9.port_b_first_address = 0,
1937 ram_block3a_9.port_b_first_bit_number = 9,
1938 ram_block3a_9.port_b_last_address = 4095,
1939 ram_block3a_9.port_b_logical_ram_depth = 4096,
1940 ram_block3a_9.port_b_logical_ram_width = 16,
1941 ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
1942 ram_block3a_9.ram_block_type = "auto",
1943 ram_block3a_9.lpm_type = "cyclone_ram_block";
1944 cyclone_ram_block ram_block3a_10
1950 .portaaddr({address_a_wire[11:0]}),
1951 .portadatain({data_a[10]}),
1954 .portbaddr({address_b_wire[11:0]}),
1955 .portbdataout(wire_ram_block3a_10portbdataout[0:0]),
1957 `ifdef FORMAL_VERIFICATION
1959 // synopsys translate_off
1964 .portabyteenamasks(1'b1),
1965 .portbbyteenamasks(1'b1),
1967 `ifdef FORMAL_VERIFICATION
1969 // synopsys translate_on
1971 // synopsys translate_off
1975 // synopsys translate_on
1978 ram_block3a_10.connectivity_checking = "OFF",
1979 ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
1980 ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
1981 ram_block3a_10.operation_mode = "dual_port",
1982 ram_block3a_10.port_a_address_width = 12,
1983 ram_block3a_10.port_a_data_width = 1,
1984 ram_block3a_10.port_a_first_address = 0,
1985 ram_block3a_10.port_a_first_bit_number = 10,
1986 ram_block3a_10.port_a_last_address = 4095,
1987 ram_block3a_10.port_a_logical_ram_depth = 4096,
1988 ram_block3a_10.port_a_logical_ram_width = 16,
1989 ram_block3a_10.port_b_address_clear = "none",
1990 ram_block3a_10.port_b_address_clock = "clock1",
1991 ram_block3a_10.port_b_address_width = 12,
1992 ram_block3a_10.port_b_data_out_clear = "none",
1993 ram_block3a_10.port_b_data_out_clock = "none",
1994 ram_block3a_10.port_b_data_width = 1,
1995 ram_block3a_10.port_b_first_address = 0,
1996 ram_block3a_10.port_b_first_bit_number = 10,
1997 ram_block3a_10.port_b_last_address = 4095,
1998 ram_block3a_10.port_b_logical_ram_depth = 4096,
1999 ram_block3a_10.port_b_logical_ram_width = 16,
2000 ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
2001 ram_block3a_10.ram_block_type = "auto",
2002 ram_block3a_10.lpm_type = "cyclone_ram_block";
2003 cyclone_ram_block ram_block3a_11
2009 .portaaddr({address_a_wire[11:0]}),
2010 .portadatain({data_a[11]}),
2013 .portbaddr({address_b_wire[11:0]}),
2014 .portbdataout(wire_ram_block3a_11portbdataout[0:0]),
2016 `ifdef FORMAL_VERIFICATION
2018 // synopsys translate_off
2023 .portabyteenamasks(1'b1),
2024 .portbbyteenamasks(1'b1),
2026 `ifdef FORMAL_VERIFICATION
2028 // synopsys translate_on
2030 // synopsys translate_off
2034 // synopsys translate_on
2037 ram_block3a_11.connectivity_checking = "OFF",
2038 ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
2039 ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
2040 ram_block3a_11.operation_mode = "dual_port",
2041 ram_block3a_11.port_a_address_width = 12,
2042 ram_block3a_11.port_a_data_width = 1,
2043 ram_block3a_11.port_a_first_address = 0,
2044 ram_block3a_11.port_a_first_bit_number = 11,
2045 ram_block3a_11.port_a_last_address = 4095,
2046 ram_block3a_11.port_a_logical_ram_depth = 4096,
2047 ram_block3a_11.port_a_logical_ram_width = 16,
2048 ram_block3a_11.port_b_address_clear = "none",
2049 ram_block3a_11.port_b_address_clock = "clock1",
2050 ram_block3a_11.port_b_address_width = 12,
2051 ram_block3a_11.port_b_data_out_clear = "none",
2052 ram_block3a_11.port_b_data_out_clock = "none",
2053 ram_block3a_11.port_b_data_width = 1,
2054 ram_block3a_11.port_b_first_address = 0,
2055 ram_block3a_11.port_b_first_bit_number = 11,
2056 ram_block3a_11.port_b_last_address = 4095,
2057 ram_block3a_11.port_b_logical_ram_depth = 4096,
2058 ram_block3a_11.port_b_logical_ram_width = 16,
2059 ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
2060 ram_block3a_11.ram_block_type = "auto",
2061 ram_block3a_11.lpm_type = "cyclone_ram_block";
2062 cyclone_ram_block ram_block3a_12
2068 .portaaddr({address_a_wire[11:0]}),
2069 .portadatain({data_a[12]}),
2072 .portbaddr({address_b_wire[11:0]}),
2073 .portbdataout(wire_ram_block3a_12portbdataout[0:0]),
2075 `ifdef FORMAL_VERIFICATION
2077 // synopsys translate_off
2082 .portabyteenamasks(1'b1),
2083 .portbbyteenamasks(1'b1),
2085 `ifdef FORMAL_VERIFICATION
2087 // synopsys translate_on
2089 // synopsys translate_off
2093 // synopsys translate_on
2096 ram_block3a_12.connectivity_checking = "OFF",
2097 ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
2098 ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
2099 ram_block3a_12.operation_mode = "dual_port",
2100 ram_block3a_12.port_a_address_width = 12,
2101 ram_block3a_12.port_a_data_width = 1,
2102 ram_block3a_12.port_a_first_address = 0,
2103 ram_block3a_12.port_a_first_bit_number = 12,
2104 ram_block3a_12.port_a_last_address = 4095,
2105 ram_block3a_12.port_a_logical_ram_depth = 4096,
2106 ram_block3a_12.port_a_logical_ram_width = 16,
2107 ram_block3a_12.port_b_address_clear = "none",
2108 ram_block3a_12.port_b_address_clock = "clock1",
2109 ram_block3a_12.port_b_address_width = 12,
2110 ram_block3a_12.port_b_data_out_clear = "none",
2111 ram_block3a_12.port_b_data_out_clock = "none",
2112 ram_block3a_12.port_b_data_width = 1,
2113 ram_block3a_12.port_b_first_address = 0,
2114 ram_block3a_12.port_b_first_bit_number = 12,
2115 ram_block3a_12.port_b_last_address = 4095,
2116 ram_block3a_12.port_b_logical_ram_depth = 4096,
2117 ram_block3a_12.port_b_logical_ram_width = 16,
2118 ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
2119 ram_block3a_12.ram_block_type = "auto",
2120 ram_block3a_12.lpm_type = "cyclone_ram_block";
2121 cyclone_ram_block ram_block3a_13
2127 .portaaddr({address_a_wire[11:0]}),
2128 .portadatain({data_a[13]}),
2131 .portbaddr({address_b_wire[11:0]}),
2132 .portbdataout(wire_ram_block3a_13portbdataout[0:0]),
2134 `ifdef FORMAL_VERIFICATION
2136 // synopsys translate_off
2141 .portabyteenamasks(1'b1),
2142 .portbbyteenamasks(1'b1),
2144 `ifdef FORMAL_VERIFICATION
2146 // synopsys translate_on
2148 // synopsys translate_off
2152 // synopsys translate_on
2155 ram_block3a_13.connectivity_checking = "OFF",
2156 ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
2157 ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
2158 ram_block3a_13.operation_mode = "dual_port",
2159 ram_block3a_13.port_a_address_width = 12,
2160 ram_block3a_13.port_a_data_width = 1,
2161 ram_block3a_13.port_a_first_address = 0,
2162 ram_block3a_13.port_a_first_bit_number = 13,
2163 ram_block3a_13.port_a_last_address = 4095,
2164 ram_block3a_13.port_a_logical_ram_depth = 4096,
2165 ram_block3a_13.port_a_logical_ram_width = 16,
2166 ram_block3a_13.port_b_address_clear = "none",
2167 ram_block3a_13.port_b_address_clock = "clock1",
2168 ram_block3a_13.port_b_address_width = 12,
2169 ram_block3a_13.port_b_data_out_clear = "none",
2170 ram_block3a_13.port_b_data_out_clock = "none",
2171 ram_block3a_13.port_b_data_width = 1,
2172 ram_block3a_13.port_b_first_address = 0,
2173 ram_block3a_13.port_b_first_bit_number = 13,
2174 ram_block3a_13.port_b_last_address = 4095,
2175 ram_block3a_13.port_b_logical_ram_depth = 4096,
2176 ram_block3a_13.port_b_logical_ram_width = 16,
2177 ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
2178 ram_block3a_13.ram_block_type = "auto",
2179 ram_block3a_13.lpm_type = "cyclone_ram_block";
2180 cyclone_ram_block ram_block3a_14
2186 .portaaddr({address_a_wire[11:0]}),
2187 .portadatain({data_a[14]}),
2190 .portbaddr({address_b_wire[11:0]}),
2191 .portbdataout(wire_ram_block3a_14portbdataout[0:0]),
2193 `ifdef FORMAL_VERIFICATION
2195 // synopsys translate_off
2200 .portabyteenamasks(1'b1),
2201 .portbbyteenamasks(1'b1),
2203 `ifdef FORMAL_VERIFICATION
2205 // synopsys translate_on
2207 // synopsys translate_off
2211 // synopsys translate_on
2214 ram_block3a_14.connectivity_checking = "OFF",
2215 ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
2216 ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
2217 ram_block3a_14.operation_mode = "dual_port",
2218 ram_block3a_14.port_a_address_width = 12,
2219 ram_block3a_14.port_a_data_width = 1,
2220 ram_block3a_14.port_a_first_address = 0,
2221 ram_block3a_14.port_a_first_bit_number = 14,
2222 ram_block3a_14.port_a_last_address = 4095,
2223 ram_block3a_14.port_a_logical_ram_depth = 4096,
2224 ram_block3a_14.port_a_logical_ram_width = 16,
2225 ram_block3a_14.port_b_address_clear = "none",
2226 ram_block3a_14.port_b_address_clock = "clock1",
2227 ram_block3a_14.port_b_address_width = 12,
2228 ram_block3a_14.port_b_data_out_clear = "none",
2229 ram_block3a_14.port_b_data_out_clock = "none",
2230 ram_block3a_14.port_b_data_width = 1,
2231 ram_block3a_14.port_b_first_address = 0,
2232 ram_block3a_14.port_b_first_bit_number = 14,
2233 ram_block3a_14.port_b_last_address = 4095,
2234 ram_block3a_14.port_b_logical_ram_depth = 4096,
2235 ram_block3a_14.port_b_logical_ram_width = 16,
2236 ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
2237 ram_block3a_14.ram_block_type = "auto",
2238 ram_block3a_14.lpm_type = "cyclone_ram_block";
2239 cyclone_ram_block ram_block3a_15
2245 .portaaddr({address_a_wire[11:0]}),
2246 .portadatain({data_a[15]}),
2249 .portbaddr({address_b_wire[11:0]}),
2250 .portbdataout(wire_ram_block3a_15portbdataout[0:0]),
2252 `ifdef FORMAL_VERIFICATION
2254 // synopsys translate_off
2259 .portabyteenamasks(1'b1),
2260 .portbbyteenamasks(1'b1),
2262 `ifdef FORMAL_VERIFICATION
2264 // synopsys translate_on
2266 // synopsys translate_off
2270 // synopsys translate_on
2273 ram_block3a_15.connectivity_checking = "OFF",
2274 ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
2275 ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
2276 ram_block3a_15.operation_mode = "dual_port",
2277 ram_block3a_15.port_a_address_width = 12,
2278 ram_block3a_15.port_a_data_width = 1,
2279 ram_block3a_15.port_a_first_address = 0,
2280 ram_block3a_15.port_a_first_bit_number = 15,
2281 ram_block3a_15.port_a_last_address = 4095,
2282 ram_block3a_15.port_a_logical_ram_depth = 4096,
2283 ram_block3a_15.port_a_logical_ram_width = 16,
2284 ram_block3a_15.port_b_address_clear = "none",
2285 ram_block3a_15.port_b_address_clock = "clock1",
2286 ram_block3a_15.port_b_address_width = 12,
2287 ram_block3a_15.port_b_data_out_clear = "none",
2288 ram_block3a_15.port_b_data_out_clock = "none",
2289 ram_block3a_15.port_b_data_width = 1,
2290 ram_block3a_15.port_b_first_address = 0,
2291 ram_block3a_15.port_b_first_bit_number = 15,
2292 ram_block3a_15.port_b_last_address = 4095,
2293 ram_block3a_15.port_b_logical_ram_depth = 4096,
2294 ram_block3a_15.port_b_logical_ram_width = 16,
2295 ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
2296 ram_block3a_15.ram_block_type = "auto",
2297 ram_block3a_15.lpm_type = "cyclone_ram_block";
2299 address_a_wire = address_a,
2300 address_b_wire = address_b,
2301 q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
2302 endmodule //fifo_4k_altsyncram_8pl
2305 //dffpipe DELAY=1 WIDTH=12 clock clrn d q
2306 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
2308 //synthesis_resources = lut 12
2309 //synopsys translate_off
2310 `timescale 1 ps / 1 ps
2311 //synopsys translate_on
2312 module fifo_4k_dffpipe_bb3
2317 q) /* synthesis synthesis_clearbox=1 */
2318 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2324 wire [11:0] wire_dffe4a_D;
2330 // synopsys translate_off
2333 // synopsys translate_on
2334 always @ ( posedge clock or negedge prn or negedge clrn)
2335 if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
2336 else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
2337 else if (ena == 1'b1) dffe4a[0:0] <= wire_dffe4a_D[0:0];
2338 // synopsys translate_off
2341 // synopsys translate_on
2342 always @ ( posedge clock or negedge prn or negedge clrn)
2343 if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
2344 else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
2345 else if (ena == 1'b1) dffe4a[1:1] <= wire_dffe4a_D[1:1];
2346 // synopsys translate_off
2349 // synopsys translate_on
2350 always @ ( posedge clock or negedge prn or negedge clrn)
2351 if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
2352 else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
2353 else if (ena == 1'b1) dffe4a[2:2] <= wire_dffe4a_D[2:2];
2354 // synopsys translate_off
2357 // synopsys translate_on
2358 always @ ( posedge clock or negedge prn or negedge clrn)
2359 if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
2360 else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
2361 else if (ena == 1'b1) dffe4a[3:3] <= wire_dffe4a_D[3:3];
2362 // synopsys translate_off
2365 // synopsys translate_on
2366 always @ ( posedge clock or negedge prn or negedge clrn)
2367 if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
2368 else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
2369 else if (ena == 1'b1) dffe4a[4:4] <= wire_dffe4a_D[4:4];
2370 // synopsys translate_off
2373 // synopsys translate_on
2374 always @ ( posedge clock or negedge prn or negedge clrn)
2375 if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
2376 else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
2377 else if (ena == 1'b1) dffe4a[5:5] <= wire_dffe4a_D[5:5];
2378 // synopsys translate_off
2381 // synopsys translate_on
2382 always @ ( posedge clock or negedge prn or negedge clrn)
2383 if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
2384 else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
2385 else if (ena == 1'b1) dffe4a[6:6] <= wire_dffe4a_D[6:6];
2386 // synopsys translate_off
2389 // synopsys translate_on
2390 always @ ( posedge clock or negedge prn or negedge clrn)
2391 if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
2392 else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
2393 else if (ena == 1'b1) dffe4a[7:7] <= wire_dffe4a_D[7:7];
2394 // synopsys translate_off
2397 // synopsys translate_on
2398 always @ ( posedge clock or negedge prn or negedge clrn)
2399 if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
2400 else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
2401 else if (ena == 1'b1) dffe4a[8:8] <= wire_dffe4a_D[8:8];
2402 // synopsys translate_off
2405 // synopsys translate_on
2406 always @ ( posedge clock or negedge prn or negedge clrn)
2407 if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
2408 else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
2409 else if (ena == 1'b1) dffe4a[9:9] <= wire_dffe4a_D[9:9];
2410 // synopsys translate_off
2413 // synopsys translate_on
2414 always @ ( posedge clock or negedge prn or negedge clrn)
2415 if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
2416 else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
2417 else if (ena == 1'b1) dffe4a[10:10] <= wire_dffe4a_D[10:10];
2418 // synopsys translate_off
2421 // synopsys translate_on
2422 always @ ( posedge clock or negedge prn or negedge clrn)
2423 if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
2424 else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
2425 else if (ena == 1'b1) dffe4a[11:11] <= wire_dffe4a_D[11:11];
2427 wire_dffe4a_D = (d & {12{(~ sclr)}});
2433 endmodule //fifo_4k_dffpipe_bb3
2436 //dffpipe WIDTH=12 clock clrn d q
2437 //VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
2440 //dffpipe WIDTH=12 clock clrn d q
2441 //VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ VERSION_END
2443 //synthesis_resources = lut 12
2444 //synopsys translate_off
2445 `timescale 1 ps / 1 ps
2446 //synopsys translate_on
2447 module fifo_4k_dffpipe_em2
2452 q) /* synthesis synthesis_clearbox=1 */
2453 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
2459 wire [11:0] wire_dffe6a_D;
2465 // synopsys translate_off
2468 // synopsys translate_on
2469 always @ ( posedge clock or negedge prn or negedge clrn)
2470 if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
2471 else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
2472 else if (ena == 1'b1) dffe6a[0:0] <= wire_dffe6a_D[0:0];
2473 // synopsys translate_off
2476 // synopsys translate_on
2477 always @ ( posedge clock or negedge prn or negedge clrn)
2478 if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
2479 else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
2480 else if (ena == 1'b1) dffe6a[1:1] <= wire_dffe6a_D[1:1];
2481 // synopsys translate_off
2484 // synopsys translate_on
2485 always @ ( posedge clock or negedge prn or negedge clrn)
2486 if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
2487 else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
2488 else if (ena == 1'b1) dffe6a[2:2] <= wire_dffe6a_D[2:2];
2489 // synopsys translate_off
2492 // synopsys translate_on
2493 always @ ( posedge clock or negedge prn or negedge clrn)
2494 if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
2495 else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
2496 else if (ena == 1'b1) dffe6a[3:3] <= wire_dffe6a_D[3:3];
2497 // synopsys translate_off
2500 // synopsys translate_on
2501 always @ ( posedge clock or negedge prn or negedge clrn)
2502 if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
2503 else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
2504 else if (ena == 1'b1) dffe6a[4:4] <= wire_dffe6a_D[4:4];
2505 // synopsys translate_off
2508 // synopsys translate_on
2509 always @ ( posedge clock or negedge prn or negedge clrn)
2510 if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
2511 else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
2512 else if (ena == 1'b1) dffe6a[5:5] <= wire_dffe6a_D[5:5];
2513 // synopsys translate_off
2516 // synopsys translate_on
2517 always @ ( posedge clock or negedge prn or negedge clrn)
2518 if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
2519 else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
2520 else if (ena == 1'b1) dffe6a[6:6] <= wire_dffe6a_D[6:6];
2521 // synopsys translate_off
2524 // synopsys translate_on
2525 always @ ( posedge clock or negedge prn or negedge clrn)
2526 if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
2527 else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
2528 else if (ena == 1'b1) dffe6a[7:7] <= wire_dffe6a_D[7:7];
2529 // synopsys translate_off
2532 // synopsys translate_on
2533 always @ ( posedge clock or negedge prn or negedge clrn)
2534 if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
2535 else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
2536 else if (ena == 1'b1) dffe6a[8:8] <= wire_dffe6a_D[8:8];
2537 // synopsys translate_off
2540 // synopsys translate_on
2541 always @ ( posedge clock or negedge prn or negedge clrn)
2542 if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
2543 else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
2544 else if (ena == 1'b1) dffe6a[9:9] <= wire_dffe6a_D[9:9];
2545 // synopsys translate_off
2548 // synopsys translate_on
2549 always @ ( posedge clock or negedge prn or negedge clrn)
2550 if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
2551 else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
2552 else if (ena == 1'b1) dffe6a[10:10] <= wire_dffe6a_D[10:10];
2553 // synopsys translate_off
2556 // synopsys translate_on
2557 always @ ( posedge clock or negedge prn or negedge clrn)
2558 if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
2559 else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
2560 else if (ena == 1'b1) dffe6a[11:11] <= wire_dffe6a_D[11:11];
2562 wire_dffe6a_D = (d & {12{(~ sclr)}});
2568 endmodule //fifo_4k_dffpipe_em2
2570 //synthesis_resources = lut 12
2571 //synopsys translate_off
2572 `timescale 1 ps / 1 ps
2573 //synopsys translate_on
2574 module fifo_4k_alt_synch_pipe_em2
2579 q) /* synthesis synthesis_clearbox=1 */
2580 /* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
2586 wire [11:0] wire_dffpipe5_q;
2588 fifo_4k_dffpipe_em2 dffpipe5
2593 .q(wire_dffpipe5_q));
2595 q = wire_dffpipe5_q;
2596 endmodule //fifo_4k_alt_synch_pipe_em2
2599 //lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
2600 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
2602 //synthesis_resources = lut 12
2603 //synopsys translate_off
2604 `timescale 1 ps / 1 ps
2605 //synopsys translate_on
2606 module fifo_4k_add_sub_b18
2610 result) /* synthesis synthesis_clearbox=1 */;
2613 output [11:0] result;
2615 wire [11:0] wire_add_sub_cella_combout;
2616 wire [0:0] wire_add_sub_cella_0cout;
2617 wire [0:0] wire_add_sub_cella_1cout;
2618 wire [0:0] wire_add_sub_cella_2cout;
2619 wire [0:0] wire_add_sub_cella_3cout;
2620 wire [0:0] wire_add_sub_cella_4cout;
2621 wire [0:0] wire_add_sub_cella_5cout;
2622 wire [0:0] wire_add_sub_cella_6cout;
2623 wire [0:0] wire_add_sub_cella_7cout;
2624 wire [0:0] wire_add_sub_cella_8cout;
2625 wire [0:0] wire_add_sub_cella_9cout;
2626 wire [0:0] wire_add_sub_cella_10cout;
2627 wire [11:0] wire_add_sub_cella_dataa;
2628 wire [11:0] wire_add_sub_cella_datab;
2630 cyclone_lcell add_sub_cella_0
2633 .combout(wire_add_sub_cella_combout[0:0]),
2634 .cout(wire_add_sub_cella_0cout[0:0]),
2635 .dataa(wire_add_sub_cella_dataa[0:0]),
2636 .datab(wire_add_sub_cella_datab[0:0]),
2638 `ifdef FORMAL_VERIFICATION
2640 // synopsys translate_off
2653 `ifdef FORMAL_VERIFICATION
2655 // synopsys translate_on
2657 // synopsys translate_off
2665 // synopsys translate_on
2668 add_sub_cella_0.cin_used = "true",
2669 add_sub_cella_0.lut_mask = "69b2",
2670 add_sub_cella_0.operation_mode = "arithmetic",
2671 add_sub_cella_0.sum_lutc_input = "cin",
2672 add_sub_cella_0.lpm_type = "cyclone_lcell";
2673 cyclone_lcell add_sub_cella_1
2675 .cin(wire_add_sub_cella_0cout[0:0]),
2676 .combout(wire_add_sub_cella_combout[1:1]),
2677 .cout(wire_add_sub_cella_1cout[0:0]),
2678 .dataa(wire_add_sub_cella_dataa[1:1]),
2679 .datab(wire_add_sub_cella_datab[1:1]),
2681 `ifdef FORMAL_VERIFICATION
2683 // synopsys translate_off
2696 `ifdef FORMAL_VERIFICATION
2698 // synopsys translate_on
2700 // synopsys translate_off
2708 // synopsys translate_on
2711 add_sub_cella_1.cin_used = "true",
2712 add_sub_cella_1.lut_mask = "69b2",
2713 add_sub_cella_1.operation_mode = "arithmetic",
2714 add_sub_cella_1.sum_lutc_input = "cin",
2715 add_sub_cella_1.lpm_type = "cyclone_lcell";
2716 cyclone_lcell add_sub_cella_2
2718 .cin(wire_add_sub_cella_1cout[0:0]),
2719 .combout(wire_add_sub_cella_combout[2:2]),
2720 .cout(wire_add_sub_cella_2cout[0:0]),
2721 .dataa(wire_add_sub_cella_dataa[2:2]),
2722 .datab(wire_add_sub_cella_datab[2:2]),
2724 `ifdef FORMAL_VERIFICATION
2726 // synopsys translate_off
2739 `ifdef FORMAL_VERIFICATION
2741 // synopsys translate_on
2743 // synopsys translate_off
2751 // synopsys translate_on
2754 add_sub_cella_2.cin_used = "true",
2755 add_sub_cella_2.lut_mask = "69b2",
2756 add_sub_cella_2.operation_mode = "arithmetic",
2757 add_sub_cella_2.sum_lutc_input = "cin",
2758 add_sub_cella_2.lpm_type = "cyclone_lcell";
2759 cyclone_lcell add_sub_cella_3
2761 .cin(wire_add_sub_cella_2cout[0:0]),
2762 .combout(wire_add_sub_cella_combout[3:3]),
2763 .cout(wire_add_sub_cella_3cout[0:0]),
2764 .dataa(wire_add_sub_cella_dataa[3:3]),
2765 .datab(wire_add_sub_cella_datab[3:3]),
2767 `ifdef FORMAL_VERIFICATION
2769 // synopsys translate_off
2782 `ifdef FORMAL_VERIFICATION
2784 // synopsys translate_on
2786 // synopsys translate_off
2794 // synopsys translate_on
2797 add_sub_cella_3.cin_used = "true",
2798 add_sub_cella_3.lut_mask = "69b2",
2799 add_sub_cella_3.operation_mode = "arithmetic",
2800 add_sub_cella_3.sum_lutc_input = "cin",
2801 add_sub_cella_3.lpm_type = "cyclone_lcell";
2802 cyclone_lcell add_sub_cella_4
2804 .cin(wire_add_sub_cella_3cout[0:0]),
2805 .combout(wire_add_sub_cella_combout[4:4]),
2806 .cout(wire_add_sub_cella_4cout[0:0]),
2807 .dataa(wire_add_sub_cella_dataa[4:4]),
2808 .datab(wire_add_sub_cella_datab[4:4]),
2810 `ifdef FORMAL_VERIFICATION
2812 // synopsys translate_off
2825 `ifdef FORMAL_VERIFICATION
2827 // synopsys translate_on
2829 // synopsys translate_off
2837 // synopsys translate_on
2840 add_sub_cella_4.cin_used = "true",
2841 add_sub_cella_4.lut_mask = "69b2",
2842 add_sub_cella_4.operation_mode = "arithmetic",
2843 add_sub_cella_4.sum_lutc_input = "cin",
2844 add_sub_cella_4.lpm_type = "cyclone_lcell";
2845 cyclone_lcell add_sub_cella_5
2847 .cin(wire_add_sub_cella_4cout[0:0]),
2848 .combout(wire_add_sub_cella_combout[5:5]),
2849 .cout(wire_add_sub_cella_5cout[0:0]),
2850 .dataa(wire_add_sub_cella_dataa[5:5]),
2851 .datab(wire_add_sub_cella_datab[5:5]),
2853 `ifdef FORMAL_VERIFICATION
2855 // synopsys translate_off
2868 `ifdef FORMAL_VERIFICATION
2870 // synopsys translate_on
2872 // synopsys translate_off
2880 // synopsys translate_on
2883 add_sub_cella_5.cin_used = "true",
2884 add_sub_cella_5.lut_mask = "69b2",
2885 add_sub_cella_5.operation_mode = "arithmetic",
2886 add_sub_cella_5.sum_lutc_input = "cin",
2887 add_sub_cella_5.lpm_type = "cyclone_lcell";
2888 cyclone_lcell add_sub_cella_6
2890 .cin(wire_add_sub_cella_5cout[0:0]),
2891 .combout(wire_add_sub_cella_combout[6:6]),
2892 .cout(wire_add_sub_cella_6cout[0:0]),
2893 .dataa(wire_add_sub_cella_dataa[6:6]),
2894 .datab(wire_add_sub_cella_datab[6:6]),
2896 `ifdef FORMAL_VERIFICATION
2898 // synopsys translate_off
2911 `ifdef FORMAL_VERIFICATION
2913 // synopsys translate_on
2915 // synopsys translate_off
2923 // synopsys translate_on
2926 add_sub_cella_6.cin_used = "true",
2927 add_sub_cella_6.lut_mask = "69b2",
2928 add_sub_cella_6.operation_mode = "arithmetic",
2929 add_sub_cella_6.sum_lutc_input = "cin",
2930 add_sub_cella_6.lpm_type = "cyclone_lcell";
2931 cyclone_lcell add_sub_cella_7
2933 .cin(wire_add_sub_cella_6cout[0:0]),
2934 .combout(wire_add_sub_cella_combout[7:7]),
2935 .cout(wire_add_sub_cella_7cout[0:0]),
2936 .dataa(wire_add_sub_cella_dataa[7:7]),
2937 .datab(wire_add_sub_cella_datab[7:7]),
2939 `ifdef FORMAL_VERIFICATION
2941 // synopsys translate_off
2954 `ifdef FORMAL_VERIFICATION
2956 // synopsys translate_on
2958 // synopsys translate_off
2966 // synopsys translate_on
2969 add_sub_cella_7.cin_used = "true",
2970 add_sub_cella_7.lut_mask = "69b2",
2971 add_sub_cella_7.operation_mode = "arithmetic",
2972 add_sub_cella_7.sum_lutc_input = "cin",
2973 add_sub_cella_7.lpm_type = "cyclone_lcell";
2974 cyclone_lcell add_sub_cella_8
2976 .cin(wire_add_sub_cella_7cout[0:0]),
2977 .combout(wire_add_sub_cella_combout[8:8]),
2978 .cout(wire_add_sub_cella_8cout[0:0]),
2979 .dataa(wire_add_sub_cella_dataa[8:8]),
2980 .datab(wire_add_sub_cella_datab[8:8]),
2982 `ifdef FORMAL_VERIFICATION
2984 // synopsys translate_off
2997 `ifdef FORMAL_VERIFICATION
2999 // synopsys translate_on
3001 // synopsys translate_off
3009 // synopsys translate_on
3012 add_sub_cella_8.cin_used = "true",
3013 add_sub_cella_8.lut_mask = "69b2",
3014 add_sub_cella_8.operation_mode = "arithmetic",
3015 add_sub_cella_8.sum_lutc_input = "cin",
3016 add_sub_cella_8.lpm_type = "cyclone_lcell";
3017 cyclone_lcell add_sub_cella_9
3019 .cin(wire_add_sub_cella_8cout[0:0]),
3020 .combout(wire_add_sub_cella_combout[9:9]),
3021 .cout(wire_add_sub_cella_9cout[0:0]),
3022 .dataa(wire_add_sub_cella_dataa[9:9]),
3023 .datab(wire_add_sub_cella_datab[9:9]),
3025 `ifdef FORMAL_VERIFICATION
3027 // synopsys translate_off
3040 `ifdef FORMAL_VERIFICATION
3042 // synopsys translate_on
3044 // synopsys translate_off
3052 // synopsys translate_on
3055 add_sub_cella_9.cin_used = "true",
3056 add_sub_cella_9.lut_mask = "69b2",
3057 add_sub_cella_9.operation_mode = "arithmetic",
3058 add_sub_cella_9.sum_lutc_input = "cin",
3059 add_sub_cella_9.lpm_type = "cyclone_lcell";
3060 cyclone_lcell add_sub_cella_10
3062 .cin(wire_add_sub_cella_9cout[0:0]),
3063 .combout(wire_add_sub_cella_combout[10:10]),
3064 .cout(wire_add_sub_cella_10cout[0:0]),
3065 .dataa(wire_add_sub_cella_dataa[10:10]),
3066 .datab(wire_add_sub_cella_datab[10:10]),
3068 `ifdef FORMAL_VERIFICATION
3070 // synopsys translate_off
3083 `ifdef FORMAL_VERIFICATION
3085 // synopsys translate_on
3087 // synopsys translate_off
3095 // synopsys translate_on
3098 add_sub_cella_10.cin_used = "true",
3099 add_sub_cella_10.lut_mask = "69b2",
3100 add_sub_cella_10.operation_mode = "arithmetic",
3101 add_sub_cella_10.sum_lutc_input = "cin",
3102 add_sub_cella_10.lpm_type = "cyclone_lcell";
3103 cyclone_lcell add_sub_cella_11
3105 .cin(wire_add_sub_cella_10cout[0:0]),
3106 .combout(wire_add_sub_cella_combout[11:11]),
3108 .dataa(wire_add_sub_cella_dataa[11:11]),
3109 .datab(wire_add_sub_cella_datab[11:11]),
3111 `ifdef FORMAL_VERIFICATION
3113 // synopsys translate_off
3126 `ifdef FORMAL_VERIFICATION
3128 // synopsys translate_on
3130 // synopsys translate_off
3138 // synopsys translate_on
3141 add_sub_cella_11.cin_used = "true",
3142 add_sub_cella_11.lut_mask = "6969",
3143 add_sub_cella_11.operation_mode = "normal",
3144 add_sub_cella_11.sum_lutc_input = "cin",
3145 add_sub_cella_11.lpm_type = "cyclone_lcell";
3147 wire_add_sub_cella_dataa = dataa,
3148 wire_add_sub_cella_datab = datab;
3150 result = wire_add_sub_cella_combout;
3151 endmodule //fifo_4k_add_sub_b18
3154 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
3155 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
3158 //lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
3159 //VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ VERSION_END
3161 //synthesis_resources = lut 104 M4K 16
3162 //synopsys translate_off
3163 `timescale 1 ps / 1 ps
3164 //synopsys translate_on
3165 module fifo_4k_dcfifo_6cq
3177 wrusedw) /* synthesis synthesis_clearbox=1 */
3178 /* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
3185 output [11:0] rdusedw;
3189 output [11:0] wrusedw;
3191 wire [11:0] wire_rdptr_g_gray2bin_bin;
3192 wire [11:0] wire_rs_dgwp_gray2bin_bin;
3193 wire [11:0] wire_wrptr_g_gray2bin_bin;
3194 wire [11:0] wire_ws_dgrp_gray2bin_bin;
3195 wire [11:0] wire_rdptr_g_q;
3196 wire [11:0] wire_rdptr_g1p_q;
3197 wire [11:0] wire_wrptr_g1p_q;
3198 wire [15:0] wire_fifo_ram_q_b;
3199 reg [11:0] delayed_wrptr_g;
3201 wire [11:0] wire_rs_brp_q;
3202 wire [11:0] wire_rs_bwp_q;
3203 wire [11:0] wire_rs_dgwp_q;
3204 wire [11:0] wire_ws_brp_q;
3205 wire [11:0] wire_ws_bwp_q;
3206 wire [11:0] wire_ws_dgrp_q;
3207 wire [11:0] wire_rdusedw_sub_result;
3208 wire [11:0] wire_wrusedw_sub_result;
3209 reg wire_rdempty_eq_comp_aeb_int;
3210 wire wire_rdempty_eq_comp_aeb;
3211 wire [11:0] wire_rdempty_eq_comp_dataa;
3212 wire [11:0] wire_rdempty_eq_comp_datab;
3213 reg wire_wrfull_eq_comp_aeb_int;
3214 wire wire_wrfull_eq_comp_aeb;
3215 wire [11:0] wire_wrfull_eq_comp_dataa;
3216 wire [11:0] wire_wrfull_eq_comp_datab;
3222 fifo_4k_a_gray2bin_9m4 rdptr_g_gray2bin
3224 .bin(wire_rdptr_g_gray2bin_bin),
3225 .gray(wire_rdptr_g_q));
3226 fifo_4k_a_gray2bin_9m4 rs_dgwp_gray2bin
3228 .bin(wire_rs_dgwp_gray2bin_bin),
3229 .gray(wire_rs_dgwp_q));
3230 fifo_4k_a_gray2bin_9m4 wrptr_g_gray2bin
3232 .bin(wire_wrptr_g_gray2bin_bin),
3234 fifo_4k_a_gray2bin_9m4 ws_dgrp_gray2bin
3236 .bin(wire_ws_dgrp_gray2bin_bin),
3237 .gray(wire_ws_dgrp_q));
3238 fifo_4k_a_graycounter_826 rdptr_g
3242 .cnt_en(valid_rdreq),
3243 .q(wire_rdptr_g_q));
3244 fifo_4k_a_graycounter_3r6 rdptr_g1p
3248 .cnt_en(valid_rdreq),
3249 .q(wire_rdptr_g1p_q));
3250 fifo_4k_a_graycounter_3r6 wrptr_g1p
3254 .cnt_en(valid_wrreq),
3255 .q(wire_wrptr_g1p_q));
3256 fifo_4k_altsyncram_8pl fifo_ram
3258 .address_a(wrptr_g),
3259 .address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
3262 .clocken1((valid_rdreq | int_rdempty)),
3264 .q_b(wire_fifo_ram_q_b),
3265 .wren_a(valid_wrreq));
3266 // synopsys translate_off
3268 delayed_wrptr_g = 0;
3269 // synopsys translate_on
3270 always @ ( posedge wrclk or posedge aclr)
3271 if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
3272 else delayed_wrptr_g <= wrptr_g;
3273 // synopsys translate_off
3276 // synopsys translate_on
3277 always @ ( posedge wrclk or posedge aclr)
3278 if (aclr == 1'b1) wrptr_g <= 12'b0;
3279 else if (valid_wrreq == 1'b1) wrptr_g <= wire_wrptr_g1p_q;
3280 fifo_4k_dffpipe_bb3 rs_brp
3284 .d(wire_rdptr_g_gray2bin_bin),
3286 fifo_4k_dffpipe_bb3 rs_bwp
3290 .d(wire_rs_dgwp_gray2bin_bin),
3292 fifo_4k_alt_synch_pipe_em2 rs_dgwp
3296 .d(delayed_wrptr_g),
3297 .q(wire_rs_dgwp_q));
3298 fifo_4k_dffpipe_bb3 ws_brp
3302 .d(wire_ws_dgrp_gray2bin_bin),
3304 fifo_4k_dffpipe_bb3 ws_bwp
3308 .d(wire_wrptr_g_gray2bin_bin),
3310 fifo_4k_alt_synch_pipe_em2 ws_dgrp
3315 .q(wire_ws_dgrp_q));
3316 fifo_4k_add_sub_b18 rdusedw_sub
3318 .dataa(wire_rs_bwp_q),
3319 .datab(wire_rs_brp_q),
3320 .result(wire_rdusedw_sub_result));
3321 fifo_4k_add_sub_b18 wrusedw_sub
3323 .dataa(wire_ws_bwp_q),
3324 .datab(wire_ws_brp_q),
3325 .result(wire_wrusedw_sub_result));
3326 always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
3327 if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab)
3329 wire_rdempty_eq_comp_aeb_int = 1'b1;
3333 wire_rdempty_eq_comp_aeb_int = 1'b0;
3336 wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
3338 wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
3339 wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
3340 always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
3341 if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab)
3343 wire_wrfull_eq_comp_aeb_int = 1'b1;
3347 wire_wrfull_eq_comp_aeb_int = 1'b0;
3350 wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
3352 wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
3353 wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
3355 int_rdempty = wire_rdempty_eq_comp_aeb,
3356 int_wrfull = wire_wrfull_eq_comp_aeb,
3357 q = wire_fifo_ram_q_b,
3358 rdempty = int_rdempty,
3359 rdusedw = wire_rdusedw_sub_result,
3360 valid_rdreq = rdreq,
3361 valid_wrreq = wrreq,
3362 wrfull = int_wrfull,
3363 wrusedw = wire_wrusedw_sub_result;
3364 endmodule //fifo_4k_dcfifo_6cq
3368 // synopsys translate_off
3369 `timescale 1 ps / 1 ps
3370 // synopsys translate_on
3382 wrusedw)/* synthesis synthesis_clearbox = 1 */;
3392 output [11:0] rdusedw;
3394 output [11:0] wrusedw;
3397 wire [11:0] sub_wire1;
3399 wire [15:0] sub_wire3;
3400 wire [11:0] sub_wire4;
3401 wire rdempty = sub_wire0;
3402 wire [11:0] wrusedw = sub_wire1[11:0];
3403 wire wrfull = sub_wire2;
3404 wire [15:0] q = sub_wire3[15:0];
3405 wire [11:0] rdusedw = sub_wire4[11:0];
3407 fifo_4k_dcfifo_6cq fifo_4k_dcfifo_6cq_component (
3414 .rdempty (sub_wire0),
3415 .wrusedw (sub_wire1),
3416 .wrfull (sub_wire2),
3418 .rdusedw (sub_wire4));
3422 // ============================================================
3423 // CNX file retrieval info
3424 // ============================================================
3425 // Retrieval info: PRIVATE: Width NUMERIC "16"
3426 // Retrieval info: PRIVATE: Depth NUMERIC "4096"
3427 // Retrieval info: PRIVATE: Clock NUMERIC "4"
3428 // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
3429 // Retrieval info: PRIVATE: Full NUMERIC "1"
3430 // Retrieval info: PRIVATE: Empty NUMERIC "1"
3431 // Retrieval info: PRIVATE: UsedW NUMERIC "1"
3432 // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
3433 // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
3434 // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
3435 // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
3436 // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
3437 // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
3438 // Retrieval info: PRIVATE: rsFull NUMERIC "0"
3439 // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
3440 // Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
3441 // Retrieval info: PRIVATE: wsFull NUMERIC "1"
3442 // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
3443 // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
3444 // Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
3445 // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
3446 // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
3447 // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
3448 // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
3449 // Retrieval info: PRIVATE: Optimize NUMERIC "2"
3450 // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
3451 // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
3452 // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3453 // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
3454 // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
3455 // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
3456 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3457 // Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
3458 // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
3459 // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
3460 // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
3461 // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
3462 // Retrieval info: CONSTANT: USE_EAB STRING "ON"
3463 // Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
3464 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
3465 // Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
3466 // Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
3467 // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
3468 // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
3469 // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
3470 // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
3471 // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
3472 // Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
3473 // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
3474 // Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
3475 // Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
3476 // Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
3477 // Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
3478 // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
3479 // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
3480 // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
3481 // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
3482 // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
3483 // Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
3484 // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
3485 // Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
3486 // Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
3487 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
3488 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
3489 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
3490 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
3491 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
3492 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
3493 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
3494 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
3495 // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE