1 // megafunction wizard: %ALTPLL%
2 // GENERATION: STANDARD
6 // ============================================================
7 // File Name: clk_doubler.v
8 // Megafunction Name(s):
10 // ============================================================
11 // ************************************************************
12 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
14 // 4.2 Build 156 11/29/2004 SJ Web Edition
15 // ************************************************************
18 //Copyright (C) 1991-2004 Altera Corporation
19 //Any megafunction design, and related netlist (encrypted or decrypted),
20 //support information, device programming or simulation file, and any other
21 //associated documentation or information provided by Altera or a partner
22 //under Altera's Megafunction Partnership Program may be used only
23 //to program PLD devices (but not masked PLD devices) from Altera. Any
24 //other use of such megafunction design, netlist, support information,
25 //device programming or simulation file, or any other related documentation
26 //or information is prohibited for any other purpose, including, but not
27 //limited to modification, reverse engineering, de-compiling, or use with
28 //any other silicon devices, unless such use is explicitly licensed under
29 //a separate agreement with Altera or a megafunction partner. Title to the
30 //intellectual property, including patents, copyrights, trademarks, trade
31 //secrets, or maskworks, embodied in any such megafunction design, netlist,
32 //support information, device programming or simulation file, or any other
33 //related documentation or information provided by Altera or a megafunction
34 //partner, remains with Altera, the megafunction partner, or their respective
35 //licensors. No other licenses, including any licenses needed under any third
36 //party's intellectual property, are provided herein.
39 // synopsys translate_off
40 `timescale 1 ps / 1 ps
41 // synopsys translate_on
50 wire [0:0] sub_wire4 = 1'h0;
51 wire [0:0] sub_wire1 = sub_wire0[0:0];
53 wire sub_wire2 = inclk0;
54 wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
56 altpll altpll_component (
59 // synopsys translate_off
84 // synopsys translate_on
87 altpll_component.clk0_duty_cycle = 50,
88 altpll_component.lpm_type = "altpll",
89 altpll_component.clk0_multiply_by = 2,
90 altpll_component.inclk0_input_frequency = 15625,
91 altpll_component.clk0_divide_by = 1,
92 altpll_component.pll_type = "AUTO",
93 altpll_component.intended_device_family = "Cyclone",
94 altpll_component.operation_mode = "NORMAL",
95 altpll_component.compensate_clock = "CLK0",
96 altpll_component.clk0_phase_shift = "0";
101 // ============================================================
102 // CNX file retrieval info
103 // ============================================================
104 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
105 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
106 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
107 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
108 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
109 // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
110 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
111 // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
112 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
113 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
114 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
115 // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
116 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
117 // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
118 // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
119 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
120 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
121 // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
122 // Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
123 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
124 // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
125 // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
126 // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
127 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
128 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
129 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
130 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
131 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
132 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
133 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
134 // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
135 // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
136 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
137 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
138 // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
139 // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
140 // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
141 // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
142 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
143 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
144 // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
145 // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
146 // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
147 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
148 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
149 // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
150 // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
151 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
152 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
153 // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
154 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
155 // Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
156 // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
157 // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
158 // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
159 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
160 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
161 // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
162 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
163 // Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
164 // Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
165 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
166 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
167 // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
168 // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
169 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
170 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
171 // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
172 // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
173 // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
174 // Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
175 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
176 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
177 // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
178 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
179 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
180 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
181 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
182 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
183 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
184 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
185 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
186 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
187 // Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
188 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
189 // Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
190 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
191 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
192 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
193 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
194 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
195 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
196 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
197 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
198 // Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE