5 input [15:0]ram_data_in,
7 output reg [15:0]ram_data_out,
8 output reg pkt_waiting,
13 /* Some parameters for usage later on */
14 parameter DATA_WIDTH = 16 ;
15 parameter NUM_PACKETS = 4 ;
17 /* Create the RAM here */
18 reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
20 /* Create the address signals */
21 reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
22 reg [7:0] usb_ram_offset ;
23 reg [1:0] usb_ram_packet ;
25 wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
28 assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
30 // Check if there is one full packet to process
31 always @(usb_ram_ain, usb_ram_aout)
35 else if (usb_ram_ain == usb_ram_aout)
36 pkt_waiting <= isfull;
37 else if (usb_ram_ain > usb_ram_aout)
38 pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
40 pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
43 // Check if there is room
44 always @(usb_ram_ain, usb_ram_aout)
48 else if (usb_ram_ain == usb_ram_aout)
49 have_space <= ~isfull;
50 else if (usb_ram_ain > usb_ram_aout)
51 have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
53 have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
56 /* RAM Write Address process */
57 always @(posedge clock_in)
64 usb_ram_ain <= usb_ram_ain + 1 ;
65 if (usb_ram_ain + 1 == usb_ram_aout)
70 /* RAM Writing process */
71 always @(posedge clock_in)
75 usb_ram[usb_ram_ain] <= ram_data_in ;
79 /* RAM Read Address process */
80 always @(posedge clock_out)
91 usb_ram_packet <= usb_ram_packet + 1 ;
95 if( usb_ram_offset == 8'b11111111 )
98 usb_ram_packet <= usb_ram_packet + 1 ;
101 usb_ram_offset <= usb_ram_offset + 1 ;
102 if (usb_ram_ain == usb_ram_aout)
106 /* RAM Reading Process */
107 always @(posedge clock_out)
109 ram_data_out <= usb_ram[usb_ram_aout] ;