11 output reg [31:0] usbdata_final,
14 reg [8:0] write_count;
17 always @(posedge usbclk)
19 if(bus_reset) // Use bus reset because this is on usbclk
21 else if(WR_fx2 & ~write_count[8])
22 write_count <= #1 write_count + 9'd1;
24 write_count <= #1 WR_fx2 ? write_count : 9'b0;
28 reg [15:0]usbdata_fixed;
30 always @(posedge usbclk)
32 WR_fx2_fixed <= WR_fx2 & ~write_count[8];
33 usbdata_fixed <= usbdata;
36 /* Used to convert 16 bits bus_data to the 32 bits wide fifo */
38 reg [15:0] usbdata_delayed ;
40 wire [31:0] usbdata_packed ;
43 always @(posedge usbclk)
50 else if (WR_fx2_fixed)
57 usbdata_delayed <= usbdata_fixed ;
65 assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
66 assign WR_packed = word_complete & writing ;
68 /* Make sure data are sync with usbclk */
69 reg [31:0]usbdata_usbclk;
72 always @(posedge usbclk)
75 usbdata_usbclk <= usbdata_packed;
76 WR_usbclk <= WR_packed;
79 /* Cross clock boundaries */
80 reg [31:0] usbdata_tx ;
85 always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
87 always @(posedge txclk)
93 always @(posedge txclk)
99 always @(posedge txclk)
104 WR_tx <= WR_1 & ~WR_2;
107 always @(posedge txclk)
115 usbdata_final <= usbdata_tx;