1 module tx_buffer_inband
3 input wire usbclk, input wire bus_reset, input wire reset,
4 input wire [15:0] usbdata, output wire have_space, input wire [3:0] channels,
5 //output transmit signals
6 output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
7 output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
8 output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
9 output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
10 input wire txclk, input wire txstrobe, input wire WR,
11 input wire clear_status, output wire tx_empty, output wire [15:0] debugbus,
13 output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
14 input wire rx_WR_enabled,
16 output wire [1:0] reg_io_enable, output wire [31:0] reg_data_in, output wire [6:0] reg_addr,
17 input wire [31:0] reg_data_out,
18 //input characteristic signals
19 input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0] rssi_2,
20 input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0] threshhold,
21 output wire [1:0] tx_underrun,
23 output wire stop, output wire [15:0] stop_time);
25 parameter NUM_CHAN = 1 ;
27 /* To generate channel readers */
30 /* These will eventually be external register */
31 reg [31:0] timestamp_clock ;
32 wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
33 wire [31:0] rssi [3:0];
34 assign rssi[0] = rssi_0;
35 assign rssi[1] = rssi_1;
36 assign rssi[2] = rssi_2;
37 assign rssi[3] = rssi_3;
39 always @(posedge txclk)
43 timestamp_clock <= timestamp_clock + 1;
46 /* Connections between tx_usb_fifo_reader and
47 cnannel/command processing blocks */
48 wire [31:0] tx_data_bus ;
49 wire [NUM_CHAN:0] chan_WR ;
50 wire [NUM_CHAN:0] chan_done ;
52 /* Connections between data block and the
54 wire [NUM_CHAN:0] chan_underrun;
55 wire [NUM_CHAN:0] chan_txempty;
57 /* Conections between tx_data_packet_fifo and
58 its reader + strobe generator */
59 wire [31:0] chan_fifodata [NUM_CHAN:0] ;
60 wire chan_pkt_waiting [NUM_CHAN:0] ;
61 wire chan_rdreq [NUM_CHAN:0] ;
62 wire chan_skip [NUM_CHAN:0] ;
63 wire chan_have_space [NUM_CHAN:0] ;
65 wire [14:0] debug [NUM_CHAN:0];
67 /* Outputs to transmit chains */
68 wire [15:0] tx_i [NUM_CHAN:0] ;
69 wire [15:0] tx_q [NUM_CHAN:0] ;
71 assign tx_i[NUM_CHAN] = 0;
72 assign tx_q[NUM_CHAN] = 0;
74 assign have_space = chan_have_space[0] & chan_have_space[1];
75 assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
77 assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
78 assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
79 assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
80 assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
82 assign tx_q_2 = 16'b0 ;
83 assign tx_i_2 = 16'b0 ;
84 assign tx_q_3 = 16'b0 ;
85 assign tx_i_3 = 16'b0 ;
86 assign tx_i_3 = 16'b0 ;
88 assign debugbus = {have_space, txclk, WR, WR_final, chan_WR, chan_done,
89 chan_pkt_waiting[0], chan_pkt_waiting[1],
90 chan_rdreq[0], chan_rdreq[1], chan_txempty[0], chan_txempty[1]};
92 wire [31:0] usbdata_final;
95 tx_packer tx_usb_packer
96 (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
97 .usbdata(usbdata), .reset(reset), .txclk(txclk),
98 .usbdata_final(usbdata_final), .WR_final(WR_final));
100 channel_demux #(NUM_CHAN) channel_demuxer
101 (.usbdata_final(usbdata_final), .WR_final(WR_final),
102 .reset(reset), .txclk(txclk), .WR_channel(chan_WR),
103 .WR_done_channel(chan_done), .ram_data(tx_data_bus));
105 generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
106 begin : generate_channel_readers
107 assign tx_underrun[i] = chan_underrun[i];
109 channel_ram tx_data_packet_fifo
110 (.reset(reset), .txclk(txclk), .datain(tx_data_bus),
111 .WR(chan_WR[i]), .WR_done(chan_done[i]),
112 .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
113 .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
114 .RD_done(chan_skip[i]));
116 chan_fifo_reader tx_chan_reader
117 (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
118 .timestamp_clock(timestamp_clock), .samples_format(4'b0),
119 .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
120 .skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
121 .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
122 .tx_empty(chan_txempty[i]), .rssi(rssi[i]), .debug(debug[i]),
123 .threshhold(threshhold), .rssi_wait(rssi_wait));
128 channel_ram tx_cmd_packet_fifo
129 (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
130 .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
131 .dataout(chan_fifodata[NUM_CHAN]), .packet_waiting(chan_pkt_waiting[NUM_CHAN]),
132 .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
134 cmd_reader tx_cmd_reader
135 (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock), .skip(chan_skip[NUM_CHAN]),
136 .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
137 .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
138 .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
139 .reg_data_in(reg_data_in), .reg_data_out(reg_data_out), .reg_addr(reg_addr),
140 .reg_io_enable(reg_io_enable), .debug(debug[NUM_CHAN]), .stop(stop), .stop_time(stop_time));
142 endmodule // tx_buffer