git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/rx_buffer_inband.v

   1 //`include "../../firmware/include/fpga_regs_common.v"
   2 //`include "../../firmware/include/fpga_regs_standard.v"
   3 module rx_buffer_inband
   4   ( input usbclk,
   5     input bus_reset,
   6     input reset,  // DSP side reset (used here), do not reset registers
   7     input reset_regs, //Only reset registers
   8     output [15:0] usbdata,
   9     input RD,
  10     output wire have_pkt_rdy,
  11     output reg rx_overrun,
  12     input wire [3:0] channels,
  13     input wire [15:0] ch_0,
  14     input wire [15:0] ch_1,
  15     input wire [15:0] ch_2,
  16     input wire [15:0] ch_3,
  17     input wire [15:0] ch_4,
  18     input wire [15:0] ch_5,
  19     input wire [15:0] ch_6,
  20     input wire [15:0] ch_7,
  21     input rxclk,
  22     input rxstrobe,
  23     input clear_status,
  24     input [6:0] serial_addr,
  25     input [31:0] serial_data,
  26     input serial_strobe,
  27     output wire [15:0] debugbus,
  28
  29         //Connection with tx_inband
  30         input rx_WR,
  31         input [15:0] rx_databus,
  32         input rx_WR_done,
  33         output reg rx_WR_enabled,
  34         //signal strength
  35         input wire [31:0] rssi_0, input wire [31:0] rssi_1,
  36         input wire [31:0] rssi_2, input wire [31:0] rssi_3,
  37     input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
  38     );
  39
  40     parameter NUM_CHAN = 1;
  41     genvar i ;
  42
  43     // FX2 Bug Fix
  44     reg [8:0] read_count;
  45     always @(negedge usbclk)
  46         if(bus_reset)
  47             read_count <= #1 9'd0;
  48         else if(RD & ~read_count[8])
  49             read_count <= #1 read_count + 9'd1;
  50         else
  51             read_count <= #1 RD ? read_count : 9'b0;
  52
  53         // Time counter
  54         reg [31:0] adctime;
  55         always @(posedge rxclk)
  56                 if (reset)
  57                         adctime <= 0;
  58                 else if (rxstrobe)
  59                         adctime <= adctime + 1;
  60
  61     // USB side fifo
  62     wire [11:0] rdusedw;
  63     wire [11:0] wrusedw;
  64     wire [15:0] fifodata;
  65     wire WR;
  66     wire have_space;
  67
  68     fifo_4kx16_dc       rx_usb_fifo (
  69              .aclr ( reset ),
  70              .data ( fifodata ),
  71              .rdclk ( ~usbclk ),
  72              .rdreq ( RD & ~read_count[8] ),
  73              .wrclk ( rxclk ),
  74              .wrreq ( WR ),
  75              .q ( usbdata ),
  76              .rdempty (  ),
  77              .rdusedw ( rdusedw ),
  78              .wrfull (  ),
  79              .wrusedw ( wrusedw ) );
  80
  81      assign have_pkt_rdy = (rdusedw >= 12'd256);
  82          assign have_space = (wrusedw < 12'd760);
  83
  84          // Rx side fifos
  85          wire chan_rdreq;
  86          wire [15:0] chan_fifodata;
  87          wire [9:0] chan_usedw;
  88          wire [NUM_CHAN:0] chan_empty;
  89          wire [3:0] rd_select;
  90          wire [NUM_CHAN:0] rx_full;
  91
  92          packet_builder #(NUM_CHAN) rx_pkt_builer (
  93              .rxclk ( rxclk ),
  94              .reset ( reset ),
  95                   .adctime ( adctime ),
  96                   .channels ( 4'd1 ),
  97              .chan_rdreq ( chan_rdreq ),
  98              .chan_fifodata ( chan_fifodata ),
  99              .chan_empty ( chan_empty ),
 100              .rd_select ( rd_select ),
 101              .chan_usedw ( chan_usedw ),
 102              .WR ( WR ),
 103              .fifodata ( fifodata ),
 104              .have_space ( have_space ),
 105                  .rssi_0(rssi_0), .rssi_1(rssi_1),
 106                 .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
 107     .overrun(tx_overrun), .underrun(tx_underrun));
 108
 109          // Detect overrun
 110          always @(posedge rxclk)
 111         if(reset)
 112             rx_overrun <= 1'b0;
 113         else if(rx_full[0])
 114             rx_overrun <= 1'b1;
 115         else if(clear_status)
 116             rx_overrun <= 1'b0;
 117
 118         reg [6:0] test;
 119         always @(posedge rxclk)
 120                 if (reset)
 121                         test <= 0;
 122                 else
 123                         test <= test + 7'd1;
 124
 125          // TODO write this genericly
 126          wire [15:0]ch[NUM_CHAN:0];
 127          assign ch[0] = ch_0;
 128
 129          wire cmd_empty;
 130          always @(posedge rxclk)
 131         if(reset)
 132             rx_WR_enabled <= 1;
 133                 else if(cmd_empty)
 134             rx_WR_enabled <= 1;
 135         else if(rx_WR_done)
 136             rx_WR_enabled <= 0;
 137
 138         wire [15:0] dataout [0:NUM_CHAN];
 139         wire [9:0]  usedw       [0:NUM_CHAN];
 140         wire empty[0:NUM_CHAN];
 141
 142          generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
 143      begin : generate_channel_fifos
 144                 wire rdreq;
 145
 146                 assign rdreq = (rd_select == i) & chan_rdreq;
 147                 //assign chan_empty[i] = usedw[i] < 10'd126;
 148         fifo_1kx16      rx_chan_fifo (
 149                  .aclr ( reset ),
 150                  .clock ( rxclk ),
 151                  .data ( ch[i] ),
 152                  .rdreq ( rdreq ),
 153                          .wrreq ( ~rx_full[i] & rxstrobe),
 154                  .empty (empty[i]),
 155                  .full (rx_full[i]),
 156                  .q ( dataout[i]),
 157              .usedw ( usedw[i]),
 158                          .almost_empty(chan_empty[i])
 159                 );
 160      end
 161      endgenerate
 162         wire [7:0] debug;
 163          fifo_1kx16 rx_cmd_fifo (
 164                  .aclr ( reset ),
 165                  .clock ( rxclk ),
 166                  .data ( rx_databus ),
 167                  .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
 168                          .wrreq ( rx_WR & rx_WR_enabled),
 169                  .empty ( cmd_empty),
 170                  .full ( rx_full[NUM_CHAN] ),
 171                  .q ( dataout[NUM_CHAN]),
 172              .usedw ( usedw[NUM_CHAN] )
 173         );
 174         assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
 175         assign chan_fifodata    = dataout[rd_select];
 176         assign chan_usedw               = usedw[rd_select];
 177     assign debugbus = {rxstrobe, chan_rdreq, debug,
 178                                 rx_full[0], chan_empty[0], empty[0], have_space, RD, rxclk};
 179 endmodule