git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/register_io.v

   1 module register_io
   2         (input clk, input reset, input wire [1:0] enable, input wire [6:0] addr,
   3          input wire [31:0] datain, output reg [31:0] dataout, output wire [15:0] debugbus,
   4          input wire [31:0] rssi_0, input wire [31:0] rssi_1,
   5          input wire [31:0] rssi_2, input wire [31:0] rssi_3,
   6          output wire [31:0] threshhold, output wire [31:0] rssi_wait);
   7
   8         reg strobe;
   9         wire [31:0] out[7:0];
  10         assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
  11         assign threshhold = out[1];
  12         assign rssi_wait = out[2];
  13
  14         always @(*)
  15         if (reset | ~enable[1])
  16            begin
  17              strobe <= 0;
  18                      dataout <= 0;
  19                    end
  20                 else
  21                    begin
  22                  if (enable[0])
  23                    begin
  24                      //read
  25                  if (addr == 7'd9)
  26                         dataout <= rssi_0;
  27                  else if (addr == 7'd10)
  28                         dataout <= rssi_1;
  29                  else if (addr == 7'd11)
  30                         dataout <= rssi_2;
  31                  else if (addr == 7'd12)
  32                         dataout <= rssi_3;
  33                  else
  34                         dataout <= out[addr[2:0]];
  35                      strobe <= 0;
  36                end
  37              else
  38                begin
  39                  //write
  40                      dataout <= dataout;
  41                  strobe <= 1;
  42                end
  43           end
  44
  45         //register declarations
  46     setting_reg #(0) setting_reg0(.clock(clk),.reset(reset),
  47     .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
  48     setting_reg #(1) setting_reg1(.clock(clk),.reset(reset),
  49     .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
  50     setting_reg #(2) setting_reg2(.clock(clk),.reset(reset),
  51     .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
  52     setting_reg #(3) setting_reg3(.clock(clk),.reset(reset),
  53     .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
  54     setting_reg #(4) setting_reg4(.clock(clk),.reset(reset),
  55     .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
  56     setting_reg #(5) setting_reg5(.clock(clk),.reset(reset),
  57     .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
  58     setting_reg #(6) setting_reg6(.clock(clk),.reset(reset),
  59     .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
  60     setting_reg #(7) setting_reg7(.clock(clk),.reset(reset),
  61     .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
  62 endmodule