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   1 module packet_builder #(parameter NUM_CHAN = 1)(
   2     // System
   3     input rxclk,
   4     input reset,
   5          input [31:0] adctime,
   6          input [3:0] channels,
   7     // ADC side
   8     input [15:0]chan_fifodata,
   9     input [NUM_CHAN:0]chan_empty,
  10     input [9:0]chan_usedw,
  11     output reg [3:0]rd_select,
  12     output reg chan_rdreq,
  13     // FX2 side
  14     output reg WR,
  15     output reg [15:0]fifodata,
  16     input have_space,
  17         input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire [31:0]rssi_2,
  18         input wire [31:0]rssi_3, output wire [7:0] debugbus,
  19         input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun);
  20
  21
  22     // States
  23     `define IDLE                     3'd0
  24     `define HEADER1                  3'd1
  25         `define HEADER2                                  3'd2
  26     `define TIMESTAMP                3'd3
  27         `define FORWARD                                  3'd4
  28
  29     `define MAXPAYLOAD 504
  30
  31     `define PAYLOAD_LEN 8:0
  32     `define TAG 12:9
  33     `define MBZ 15:13
  34
  35     `define CHAN 4:0
  36     `define RSSI 10:5
  37     `define BURST 12:11
  38     `define DROPPED 13
  39     `define UNDERRUN 14
  40     `define OVERRUN 15
  41
  42     reg [2:0] state;
  43     reg [8:0] read_length;
  44     reg [8:0] payload_len;
  45     reg tstamp_complete;
  46     reg [3:0] check_next;
  47         wire [8:0] chan_used;
  48     wire [31:0] true_rssi;
  49         wire [4:0] true_channel;
  50
  51         assign debugbus = {state, chan_empty[0], underrun[0], check_next[0],
  52                                                 have_space, rd_select[0]};
  53         assign chan_used = chan_usedw[8:0];
  54         assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
  55                                                         ((rd_select[0]) ? rssi_1:rssi_0);
  56         assign true_channel = (check_next == 4'd0 ? 5'h1f : {1'd0, check_next - 4'd1});
  57     always @(posedge rxclk)
  58     begin
  59         if (reset)
  60           begin
  61             WR <= 0;
  62             rd_select <= 0;
  63             chan_rdreq <= 0;
  64             tstamp_complete <= 0;
  65             check_next <= 0;
  66             state <= `IDLE;
  67           end
  68         else case (state)
  69             `IDLE: begin
  70                                 chan_rdreq <= #1 0;
  71                                 if (have_space)
  72                                   begin
  73                                         if(~chan_empty[check_next])
  74                                       begin
  75                                 state <= #1 `HEADER1;
  76                                                 rd_select <= #1 check_next;
  77                                           end
  78                                         check_next <= #1 (check_next == channels ? 4'd0 : check_next + 4'd1);
  79                                   end
  80             end
  81
  82             `HEADER1: begin
  83                 fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252
  84                                            ? 9'd252 : chan_used << 1);
  85                 payload_len <= #1 (chan_used > 9'd252
  86                                 ? 9'd252 : chan_used << 1);
  87                 fifodata[`TAG] <= #1 0;
  88                 fifodata[`MBZ] <= #1 0;
  89                 WR <= #1 1;
  90
  91                 state <= #1 `HEADER2;
  92                 read_length <= #1 0;
  93             end
  94
  95             `HEADER2: begin
  96                 fifodata[`CHAN] <= #1 true_channel;
  97                 fifodata[`RSSI] <= #1 true_rssi[5:0];
  98                 fifodata[`BURST] <= #1 0;
  99                 fifodata[`DROPPED] <= #1 0;
 100                 fifodata[`UNDERRUN] <= #1 (check_next == 0) ? 1'b0 : underrun[true_channel];
 101                 fifodata[`OVERRUN] <= #1 (check_next == 0) ? 1'b0 : overrun[true_channel];
 102                 state <= #1 `TIMESTAMP;
 103             end
 104
 105             `TIMESTAMP: begin
 106                 fifodata <= #1 (tstamp_complete ? adctime[31:16] : adctime[15:0]);
 107                 tstamp_complete <= #1 ~tstamp_complete;
 108
 109                 if (~tstamp_complete)
 110                     chan_rdreq <= #1 1;
 111
 112                 state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
 113             end
 114
 115             `FORWARD: begin
 116                 read_length <= #1 read_length + 9'd2;
 117                 fifodata <= #1 (read_length >= payload_len ? 16'hDEAD : chan_fifodata);
 118
 119                 if (read_length >= `MAXPAYLOAD)
 120                   begin
 121                     WR <= #1 0;
 122                     state <= #1 `IDLE;
 123                                         chan_rdreq <= #1 0;
 124                   end
 125                 else if (read_length == payload_len - 4)
 126                     chan_rdreq <= #1 0;
 127             end
 128
 129             default: begin
 130                                 //handling error state
 131                 state <= `IDLE;
 132             end
 133             endcase
 134     end
 135 endmodule
 136