git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/data_packet_fifo.v

   1 module data_packet_fifo
   2   ( input       reset,
   3     input       clock,
   4     input       [31:0]ram_data_in,
   5     input       write_enable,
   6     output  reg have_space,
   7     output  reg [31:0]ram_data_out,
   8     output  reg pkt_waiting,
   9         output  reg     isfull,
  10         output  reg [1:0]usb_ram_packet_out,
  11         output  reg [1:0]usb_ram_packet_in,
  12     input       read_enable,
  13     input       pkt_complete,
  14     input       skip_packet) ;
  15
  16     /* Some parameters for usage later on */
  17     parameter DATA_WIDTH = 32 ;
  18     parameter PKT_DEPTH = 128 ;
  19     parameter NUM_PACKETS = 4 ;
  20
  21     /* Create the RAM here */
  22     reg [DATA_WIDTH-1:0] usb_ram [PKT_DEPTH*NUM_PACKETS-1:0] ;
  23
  24     /* Create the address signals */
  25     reg [6:0] usb_ram_offset_out ;
  26     //reg [1:0] usb_ram_packet_out ;
  27     reg [6:0] usb_ram_offset_in ;
  28     //reg [1:0] usb_ram_packet_in ;
  29
  30     wire [6-2+NUM_PACKETS:0] usb_ram_aout ;
  31     wire [6-2+NUM_PACKETS:0] usb_ram_ain ;
  32     //reg isfull;
  33
  34     assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
  35     assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
  36
  37     // Check if there is one full packet to process
  38     always @(usb_ram_ain, usb_ram_aout, isfull)
  39     begin
  40         if (usb_ram_ain == usb_ram_aout)
  41             pkt_waiting <= isfull ;
  42         else if (usb_ram_ain > usb_ram_aout)
  43             pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= PKT_DEPTH;
  44         else
  45             pkt_waiting <= (usb_ram_ain + 10'b1000000000 - usb_ram_aout) >= PKT_DEPTH;
  46     end
  47
  48     // Check if there is room
  49     always @(usb_ram_ain, usb_ram_aout, isfull)
  50     begin
  51         if (usb_ram_ain == usb_ram_aout)
  52             have_space <= ~isfull;
  53         else if (usb_ram_ain > usb_ram_aout)
  54             have_space <= ((usb_ram_ain - usb_ram_aout) <= PKT_DEPTH * (NUM_PACKETS - 1))? 1'b1 : 1'b0;
  55         else
  56             have_space <= (usb_ram_aout - usb_ram_ain) >= PKT_DEPTH;
  57     end
  58
  59
  60
  61     /* RAM Writing/Reading process */
  62     always @(posedge clock)
  63     begin
  64         if( write_enable )
  65           begin
  66             usb_ram[usb_ram_ain] <= ram_data_in ;
  67           end
  68                 ram_data_out <= usb_ram[usb_ram_aout] ;
  69     end
  70
  71     /* RAM Write/Read Address process */
  72     always @(posedge clock)
  73     begin
  74         if( reset )
  75           begin
  76             usb_ram_packet_out <= 0 ;
  77             usb_ram_offset_out <= 0 ;
  78                         usb_ram_offset_in <= 0 ;
  79             usb_ram_packet_in <= 0 ;
  80             isfull <= 0;
  81           end
  82         else
  83                   begin
  84             if( skip_packet )
  85               begin
  86                 usb_ram_packet_out <= usb_ram_packet_out + 1 ;
  87                 usb_ram_offset_out <= 0 ;
  88                 isfull <= 0;
  89               end
  90             else if(read_enable)
  91                           begin
  92                 if( usb_ram_offset_out == 7'b1111111 )
  93                   begin
  94                     isfull <= 0 ;
  95                     usb_ram_offset_out <= 0 ;
  96                     usb_ram_packet_out <= usb_ram_packet_out + 1 ;
  97                   end
  98                 else
  99                     usb_ram_offset_out <= usb_ram_offset_out + 1 ;
 100               end
 101                         if( pkt_complete )
 102               begin
 103                 usb_ram_packet_in <= usb_ram_packet_in + 1 ;
 104                 usb_ram_offset_in <= 0 ;
 105                 if ((usb_ram_packet_in + 2'b1) == usb_ram_packet_out)
 106                     isfull <= 1 ;
 107               end
 108             else if( write_enable )
 109               begin
 110                 if (usb_ram_offset_in == 7'b1111111)
 111                     usb_ram_offset_in <= 7'b1111111 ;
 112                 else
 113                     usb_ram_offset_in <= usb_ram_offset_in + 1 ;
 114               end
 115                   end
 116     end
 117
 118 endmodule