git.gag.com Git - debian/gnuradio/blob - usrp/fpga/inband_lib/data_packet_fifo.v

   1 module data_packet_fifo
   2   ( input       reset,
   3     input       clock,
   4     input       [15:0]ram_data_in,
   5     input       write_enable,
   6     output  reg have_space,
   7     output  reg [15:0]ram_data_out,
   8     output  reg pkt_waiting,
   9     input       read_enable,
  10     input       pkt_complete,
  11     input       skip_packet) ;
  12
  13     /* Some parameters for usage later on */
  14     parameter DATA_WIDTH = 16 ;
  15     parameter NUM_PACKETS = 4 ;
  16
  17     /* Create the RAM here */
  18     reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
  19
  20     /* Create the address signals */
  21     reg [7:0] usb_ram_offset_out ;
  22     reg [1:0] usb_ram_packet_out ;
  23     reg [7:0] usb_ram_offset_in ;
  24     reg [1:0] usb_ram_packet_in ;
  25
  26     wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
  27     wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
  28     reg isfull;
  29
  30     assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
  31     assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
  32
  33     // Check if there is one full packet to process
  34     always @(usb_ram_ain, usb_ram_aout)
  35     begin
  36         if (reset)
  37             pkt_waiting <= 0;
  38         else if (usb_ram_ain >= usb_ram_aout)
  39             pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
  40         else
  41             pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
  42     end
  43
  44     // Check if there is room
  45     always @(usb_ram_ain, usb_ram_aout)
  46     begin
  47         if (reset)
  48             have_space <= 1;
  49         else if (usb_ram_ain == usb_ram_aout)
  50             have_space <= ~isfull;
  51         else if (usb_ram_ain > usb_ram_aout)
  52             have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
  53         else
  54             have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
  55     end
  56
  57     /* RAM Write Address process */
  58     always @(posedge clock)
  59     begin
  60         if( reset )
  61           begin
  62             usb_ram_offset_in <= 0 ;
  63             usb_ram_packet_in <= 0 ;
  64           end
  65         else
  66             if( pkt_complete )
  67               begin
  68                 usb_ram_packet_in <= usb_ram_packet_in + 1;
  69                 usb_ram_offset_in <= 0;
  70               end
  71             else if( write_enable )
  72               begin
  73                 if (usb_ram_offset_in == 8'b11111111)
  74                   begin
  75                     usb_ram_offset_in <= 0;
  76                     usb_ram_packet_in <= usb_ram_packet_in + 1;
  77                   end
  78                 else
  79                     usb_ram_offset_in <= usb_ram_offset_in + 1 ;
  80                     if (usb_ram_ain + 1 == usb_ram_aout)
  81                        isfull <= 1;
  82               end
  83     end
  84
  85     /* RAM Writing process */
  86     always @(posedge clock)
  87     begin
  88         if( write_enable )
  89           begin
  90             usb_ram[usb_ram_ain] <= ram_data_in ;
  91           end
  92     end
  93
  94     /* RAM Read Address process */
  95     always @(posedge clock)
  96     begin
  97         if( reset )
  98           begin
  99             usb_ram_packet_out <= 0 ;
 100             usb_ram_offset_out <= 0 ;
 101             isfull <= 0;
 102           end
 103         else
 104             if( skip_packet )
 105               begin
 106                 usb_ram_packet_out <= usb_ram_packet_out + 1 ;
 107                 usb_ram_offset_out <= 0 ;
 108               end
 109             else if(read_enable) begin
 110                 if( usb_ram_offset_out == 8'b11111111 )
 111                   begin
 112                     usb_ram_offset_out <= 0 ;
 113                     usb_ram_packet_out <= usb_ram_packet_out + 1 ;
 114                   end
 115                 else
 116                     usb_ram_offset_out <= usb_ram_offset_out + 1 ;
 117             end
 118             if (usb_ram_ain == usb_ram_aout)
 119                isfull <= 0;
 120     end
 121
 122     /* RAM Reading Process */
 123     always @(posedge clock)
 124     begin
 125         ram_data_out <= usb_ram[usb_ram_aout] ;
 126     end
 127
 128 endmodule