3 input reset, input txclk, input [31:0] timestamp_clock,
5 output reg skip, output reg rdreq,
6 input [31:0] fifodata, input pkt_waiting,
8 input rx_WR_enabled, output reg [15:0] rx_databus,
9 output reg rx_WR, output reg rx_WR_done,
11 input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
12 output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
13 output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
16 parameter IDLE = 4'd0;
17 parameter HEADER = 4'd1;
18 parameter TIMESTAMP = 4'd2;
19 parameter WAIT = 4'd3;
20 parameter TEST = 4'd4;
21 parameter SEND = 4'd5;
22 parameter PING = 4'd6;
23 parameter WRITE_REG = 4'd7;
24 parameter WRITE_REG_MASKED = 4'd8;
25 parameter READ_REG = 4'd9;
26 parameter DELAY = 4'd14;
28 `define OP_PING_FIXED 8'd0
29 `define OP_PING_FIXED_REPLY 8'd1
30 `define OP_WRITE_REG 8'd2
31 `define OP_WRITE_REG_MASKED 8'd3
32 `define OP_READ_REG 8'd4
33 `define OP_READ_REG_REPLY 8'd5
34 `define OP_DELAY 8'd12
37 reg [6:0] payload_read;
47 reg [1:0] lines_out_total;
54 assign ops = value0[`OP_CODE];
55 assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled, value0[2:0], ops[2:0]};
57 always @(posedge txclk)
85 payload <= fifodata[`PAYLOAD];
99 if ((value0 <= timestamp_clock + `JITTER
100 && value0 > timestamp_clock)
101 || value0 == 32'hFFFFFFFF)
103 // Wait a little bit more
104 else if (value0 > timestamp_clock + `JITTER)
107 else if (value0 < timestamp_clock)
120 if (payload_read == payload)
131 payload_read <= payload_read + 7'd1;
133 case (fifodata[`OP_CODE])
143 `OP_WRITE_REG_MASKED:
145 state <= WRITE_REG_MASKED;
158 //error, skip this packet
175 if (lines_out == lines_out_total)
195 lines_out <= lines_out + 2'd1;
207 lines_out_total <= 2'd1;
210 high <= {`OP_PING_FIXED_REPLY, 8'd2};
219 lines_out_total <= 2'd2;
224 high <= {`OP_READ_REG_REPLY, 8'd6};
226 reg_io_enable <= 2'd3;
227 reg_addr <= value0[6:0];
231 high <= reg_data_out[31:16];
232 low <= reg_data_out[15:0];
243 if (lines_in == 2'd1)
245 payload_read <= payload_read + 7'd1;
246 lines_in <= lines_in + 2'd1;
252 reg_io_enable <= 2'd2;
253 reg_data_in <= value1;
254 reg_addr <= value0[6:0];
267 if (lines_in == 2'd1)
270 payload_read <= payload_read + 7'd1;
271 lines_in <= lines_in + 2'd1;
274 else if (lines_in == 2'd2)
277 payload_read <= payload_read + 7'd1;
278 lines_in <= lines_in + 2'd1;
283 reg_io_enable <= 2'd2;
284 reg_data_in <= (value1 & value2);
285 reg_addr <= value0[6:0];
295 stop_time <= value0[15:0];
301 //error state handling