3 input txclk, input reset,
5 input [31:0] datain, input WR, input WR_done, output have_space,
7 output [31:0] dataout, input RD, input RD_done, output packet_waiting);
9 reg [6:0] wr_addr, rd_addr;
10 reg [1:0] which_ram_wr, which_ram_rd;
13 reg [31:0] ram0 [0:127];
14 reg [31:0] ram1 [0:127];
15 reg [31:0] ram2 [0:127];
16 reg [31:0] ram3 [0:127];
25 wire [6:0] rd_addr_final;
26 wire [1:0] which_ram_rd_final;
29 always @(posedge txclk)
30 if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
32 always @(posedge txclk)
33 if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
35 always @(posedge txclk)
36 if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
38 always @(posedge txclk)
39 if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
41 assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
43 always @(posedge txclk)
49 wr_addr <= wr_addr + 7'd1;
51 always @(posedge txclk)
55 which_ram_wr <= which_ram_wr + 2'd1;
57 assign have_space = (nb_packets < 3'd3);
61 // rd_addr_final is what rd_addr is going to be next clock cycle
62 // which_ram_rd_final is what which_ram_rd is going to be next clock cycle
63 always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
64 always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
65 always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
66 always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
68 assign dataout = (which_ram_rd_final[1]) ?
69 (which_ram_rd_final[0] ? dataout3 : dataout2) :
70 (which_ram_rd_final[0] ? dataout1 : dataout0);
72 //RD_done is the only way to signal the end of one packet
73 assign rd_done_int = RD_done;
75 always @(posedge txclk)
81 rd_addr <= rd_addr + 7'd1;
83 assign rd_addr_final = (reset|RD_done) ? (6'd0) :
84 ((RD)?(rd_addr+7'd1):rd_addr);
86 always @(posedge txclk)
90 which_ram_rd <= which_ram_rd + 2'd1;
92 assign which_ram_rd_final = (reset) ? (2'd0):
93 ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
95 //packet_waiting is set to zero if rd_done_int is high
96 //because there is no guarantee that nb_packets will be pos.
98 assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
99 always @(posedge txclk)
102 else if (wr_done_int & ~rd_done_int)
103 nb_packets <= nb_packets + 3'd1;
104 else if (rd_done_int & ~wr_done_int)
105 nb_packets <= nb_packets - 3'd1;