13 output [31:0] dataout,
16 output packet_waiting);
18 reg [6:0] wr_addr, rd_addr;
19 reg [1:0] which_ram_wr, which_ram_rd;
22 reg [31:0] ram0 [0:127];
23 reg [31:0] ram1 [0:127];
24 reg [31:0] ram2 [0:127];
25 reg [31:0] ram3 [0:127];
34 wire [6:0] rd_addr_final;
35 wire [1:0] which_ram_rd_final;
38 always @(posedge txclk)
39 if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
41 always @(posedge txclk)
42 if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
44 always @(posedge txclk)
45 if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
47 always @(posedge txclk)
48 if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
50 assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
52 always @(posedge txclk)
58 wr_addr <= wr_addr + 7'd1;
60 always @(posedge txclk)
64 which_ram_wr <= which_ram_wr + 2'd1;
66 assign have_space = (nb_packets < 3'd3);
70 // rd_addr_final is what rd_addr is going to be next clock cycle
71 // which_ram_rd_final is what which_ram_rd is going to be next clock cycle
72 always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
73 always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
74 always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
75 always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
77 assign dataout = (which_ram_rd_final[1]) ?
78 (which_ram_rd_final[0] ? dataout3 : dataout2) :
79 (which_ram_rd_final[0] ? dataout1 : dataout0);
81 //RD_done is the only way to signal the end of one packet
82 assign rd_done_int = RD_done;
84 always @(posedge txclk)
89 else if (RD) rd_addr <= rd_addr + 7'd1;
91 assign rd_addr_final = (reset|RD_done) ? (6'd0) :
92 ((RD)?(rd_addr+7'd1):rd_addr);
93 always @(posedge txclk)
97 which_ram_rd <= which_ram_rd + 2'd1;
99 assign which_ram_rd_final = (reset) ? (2'd0):
100 ((rd_done_int) ? (which_ram_rd + 2'd1) : which_ram_rd);
102 //packet_waiting is set to zero if rd_done_int is high
103 //because there is no guarantee that nb_packets will be pos.
104 //assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
105 assign packet_waiting = (nb_packets > 1) | ((nb_packets == 1)&(~rd_done_int));
106 always @(posedge txclk)
109 else if (wr_done_int & ~rd_done_int)
110 nb_packets <= nb_packets + 3'd1;
111 else if (rd_done_int & ~wr_done_int)
112 nb_packets <= nb_packets - 3'd1;