2 #(parameter NUM_CHAN = 2) ( //usb Side
3 input [31:0]usbdata_final,
8 output reg [NUM_CHAN:0] WR_channel,
9 output reg [31:0] ram_data,
10 output reg [NUM_CHAN:0] WR_done_channel );
11 /* Parse header and forward to ram */
13 reg [2:0]reader_state;
15 reg [6:0]read_length ;
18 parameter IDLE = 3'd0;
19 parameter HEADER = 3'd1;
20 parameter WAIT = 3'd2;
21 parameter FORWARD = 3'd3;
25 wire [4:0] true_channel;
26 assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
27 NUM_CHAN : (usbdata_final[`CHANNEL]);
29 always @(posedge txclk)
41 reader_state <= HEADER;
44 // Store channel and forware header
46 channel <= true_channel;
47 WR_channel[true_channel] <= 1;
48 ram_data <= usbdata_final;
55 WR_channel[channel] <= 0;
57 if (read_length == `PKT_SIZE)
60 reader_state <= FORWARD;
64 WR_channel[channel] <= 1;
65 ram_data <= usbdata_final;
66 read_length <= read_length + 7'd1;