1 module chan_fifo_reader
2 ( reset, tx_clock, tx_strobe, adc_time, samples_format,
3 fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
4 underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
8 input wire tx_strobe ; //signal to output tx_i and tx_q
9 input wire [31:0] adc_time ; //current time
10 input wire [3:0] samples_format ;// not useful at this point
11 input wire [31:0] fifodata ; //the data input
12 input wire pkt_waiting ; //signal the next packet is ready
13 output reg rdreq ; //actually an ack to the current fifodata
14 output reg skip ; //finish reading current packet
15 output reg [15:0] tx_q ; //top 16 bit output of fifodata
16 output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
18 output reg tx_empty ; //cause 0 to be the output
19 input wire [31:0] rssi;
20 input wire [31:0] threshhold;
21 input wire [31:0] rssi_wait;
23 output wire [14:0] debug;
24 assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]};
25 // Should not be needed if adc clock rate < tx clock rate
30 // 16 bits interleaved complex samples
34 parameter IDLE = 3'd0;
35 parameter HEADER = 3'd1;
36 parameter TIMESTAMP = 3'd2;
37 parameter WAIT = 3'd3;
38 parameter WAITSTROBE = 3'd4;
39 parameter SEND = 3'd5;
44 `define STARTOFBURST 28
49 reg [2:0] reader_state;
51 reg [6:0] payload_len;
59 always @(posedge tx_clock)
81 * reset all the variables and wait for a tx_strobe
82 * it is assumed that the ram connected to this fifo_reader
83 * is a short hand fifo meaning that the header to the next packet
84 * is already available to this fifo_reader when pkt_waiting is on
90 reader_state <= HEADER;
94 if (burst == 1 && pkt_waiting == 0)
107 rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
108 //Check Start/End burst flag
109 if (fifodata[`STARTOFBURST] == 1
110 && fifodata[`ENDOFBURST] == 1)
112 else if (fifodata[`STARTOFBURST] == 1)
114 else if (fifodata[`ENDOFBURST] == 1)
117 if (trash == 1 && fifodata[`STARTOFBURST] == 0)
120 reader_state <= IDLE;
125 payload_len <= fifodata[`PAYLOAD] ;
128 reader_state <= TIMESTAMP;
134 timestamp <= fifodata;
135 reader_state <= WAIT;
141 // Decide if we wait, send or discard samples
147 time_wait <= time_wait + 32'd1;
149 if ((timestamp < adc_time) ||
150 (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
153 reader_state <= IDLE;
157 else if ((timestamp <= adc_time + `JITTER
158 && timestamp > adc_time)
159 || timestamp == 32'hFFFFFFFF)
161 if (rssi <= threshhold || rssi_flag == 0)
164 reader_state <= WAITSTROBE;
167 reader_state <= WAIT;
170 reader_state <= WAIT;
171 // Wait a little bit more
172 //else if (timestamp > adc_time + `JITTER)
173 // reader_state <= WAIT;
176 // Wait for the transmit chain to be ready
179 // If end of payload...
180 if (read_len == payload_len)
182 reader_state <= IDLE;
187 else if (tx_strobe == 1)
189 reader_state <= SEND;
194 // Send the samples to the tx_chain
197 reader_state <= WAITSTROBE;
198 read_len <= read_len + 7'd1;
205 tx_i <= fifodata[15:0];
206 tx_q <= fifodata[31:16];
209 // Assume 16 bits complex samples by default
212 tx_i <= fifodata[15:0];
213 tx_q <= fifodata[31:16];
221 reader_state <= IDLE;