2 * USRP - Universal Software Radio Peripheral
4 * Copyright (C) 2003 Free Software Foundation, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
22 * These are the register definitions for the Rev 1 USRP prototype
23 * The Rev 1 is the version with the AD9862's and daughterboards
26 #ifndef _USRP_REV1_REGS_H_
27 #define _USRP_REV1_REGS_H_
32 * Port A (bit addressable):
35 #define USRP_PA IOA // Port A
36 #define USRP_PA_OE OEA // Port A direction register
38 #define bmPA_S_CLK bmBIT0 // SPI serial clock
39 #define bmPA_S_DATA_TO_PERIPH bmBIT1 // SPI SDI (peripheral rel name)
40 #define bmPA_S_DATA_FROM_PERIPH bmBIT2 // SPI SDO (peripheral rel name)
41 #define bmPA_SEN_FPGA bmBIT3 // serial enable for FPGA (active low)
42 #define bmPA_SEN_CODEC_A bmBIT4 // serial enable AD9862 A (active low)
43 #define bmPA_SEN_CODEC_B bmBIT5 // serial enable AD9862 B (active low)
44 //#define bmPA_FX2_2 bmBIT6 // misc pin to FPGA (overflow)
45 //#define bmPA_FX2_3 bmBIT7 // misc pin to FPGA (underflow)
46 #define bmPA_RX_OVERRUN bmBIT6 // misc pin to FPGA (overflow)
47 #define bmPA_TX_UNDERRUN bmBIT7 // misc pin to FPGA (underflow)
50 sbit at 0x80+0 bitS_CLK; // 0x80 is the bit address of PORT A
51 sbit at 0x80+1 bitS_OUT; // out from FX2 point of view
52 sbit at 0x80+2 bitS_IN; // in from FX2 point of view
55 /* all outputs except S_DATA_FROM_PERIPH, FX2_2, FX2_3 */
57 #define bmPORT_A_OUTPUTS (bmPA_S_CLK \
58 | bmPA_S_DATA_TO_PERIPH \
64 #define bmPORT_A_INITIAL (bmPA_SEN_FPGA | bmPA_SEN_CODEC_A | bmPA_SEN_CODEC_B)
67 /* Port B: GPIF FD[7:0] */
70 * Port C (bit addressable):
71 * 5:1 FPGA configuration
74 #define USRP_PC IOC // Port C
75 #define USRP_PC_OE OEC // Port C direction register
77 #define USRP_ALTERA_CONFIG USRP_PC
79 #define bmPC_nRESET bmBIT0 // reset line to codecs (active low)
80 #define bmALTERA_DATA0 bmBIT1
81 #define bmALTERA_NCONFIG bmBIT2
82 #define bmALTERA_DCLK bmBIT3
83 #define bmALTERA_CONF_DONE bmBIT4
84 #define bmALTERA_NSTATUS bmBIT5
85 #define bmPC_LED0 bmBIT6 // active low
86 #define bmPC_LED1 bmBIT7 // active low
88 sbit at 0xA0+1 bitALTERA_DATA0; // 0xA0 is the bit address of PORT C
89 sbit at 0xA0+3 bitALTERA_DCLK;
92 #define bmALTERA_BITS (bmALTERA_DATA0 \
95 | bmALTERA_CONF_DONE \
98 #define bmPORT_C_OUTPUTS (bmPC_nRESET \
106 #define bmPORT_C_INITIAL (bmPC_LED0 | bmPC_LED1)
109 #define USRP_LED_REG USRP_PC
110 #define bmLED0 bmPC_LED0
111 #define bmLED1 bmPC_LED1
114 /* Port D: GPIF FD[15:8] */
116 /* Port E: not bit addressible */
118 #define USRP_PE IOE // Port E
119 #define USRP_PE_OE OEE // Port E direction register
121 #define bmPE_PE0 bmBIT0 // GPIF debug output
122 #define bmPE_PE1 bmBIT1 // GPIF debug output
123 #define bmPE_PE2 bmBIT2 // GPIF debug output
124 #define bmPE_FPGA_CLR_STATUS bmBIT3 // misc pin to FPGA (clear status)
125 #define bmPE_SEN_TX_A bmBIT4 // serial enable d'board TX A (active low)
126 #define bmPE_SEN_RX_A bmBIT5 // serial enable d'board RX A (active low)
127 #define bmPE_SEN_TX_B bmBIT6 // serial enable d'board TX B (active low)
128 #define bmPE_SEN_RX_B bmBIT7 // serial enable d'board RX B (active low)
131 #define bmPORT_E_OUTPUTS (bmPE_FPGA_CLR_STATUS \
139 #define bmPORT_E_INITIAL (bmPE_SEN_TX_A \
146 * FPGA output lines that are tied to FX2 RDYx inputs.
147 * These are readable using GPIFREADYSTAT.
149 #define bmFPGA_HAS_SPACE bmBIT0 // usbrdy[0] has room for 512 byte packet
150 #define bmFPGA_PKT_AVAIL bmBIT1 // usbrdy[1] has >= 512 bytes available
151 // #define bmTX_UNDERRUN bmBIT2 // usbrdy[2] D/A ran out of data
152 // #define bmRX_OVERRUN bmBIT3 // usbrdy[3] A/D ran out of buffer
155 * FPGA input lines that are tied to the FX2 CTLx outputs.
157 * These are controlled by the GPIF microprogram...
159 // WR bmBIT0 // usbctl[0]
160 // RD bmBIT1 // usbctl[1]
161 // OE bmBIT2 // usbctl[2]
163 #endif /* _USRP_REV1_REGS_H_ */