1 // This program configures the General Programmable Interface (GPIF) for FX2.
2 // Please do not modify sections of text which are marked as "DO NOT EDIT ...".
6 // Interface Timing Async
7 // Internal Ready Init IntRdy=1
8 // CTL Out Tristate-able Binary
9 // SingleWrite WF Select 1
10 // SingleRead WF Select 0
11 // FifoWrite WF Select 3
12 // FifoRead WF Select 2
13 // Data Bus Idle Drive Tristate
23 // GPIF Ctrl Outputs Level
28 // CTL 4 = unused CMOS
38 // FIFOFlag = FIFOFlag
39 // IntReady = IntReady
43 // GPIF Waveform 0: singlerd
45 // Interval 0 1 2 3 4 5 6 Idle (7)
46 // _________ _________ _________ _________ _________ _________ _________ _________
48 // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
49 // DataMode NO Data NO Data NO Data NO Data NO Data NO Data NO Data
50 // NextData SameData SameData SameData SameData SameData SameData SameData
51 // Int Trig No Int No Int No Int No Int No Int No Int No Int
52 // IF/Wait Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
59 // Sngl/CRC Default Default Default Default Default Default Default
60 // WEN# 0 0 0 0 0 0 0 0
61 // REN# 0 0 0 0 0 0 0 0
62 // OE# 0 0 0 0 0 0 0 0
63 // CLRST 0 0 0 0 0 0 0 0
64 // unused 0 0 0 0 0 0 0 0
65 // BOGUS 0 0 0 0 0 0 0 0
70 // GPIF Waveform 1: singlewr
72 // Interval 0 1 2 3 4 5 6 Idle (7)
73 // _________ _________ _________ _________ _________ _________ _________ _________
75 // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
76 // DataMode Activate Activate Activate Activate Activate Activate Activate
77 // NextData SameData SameData SameData SameData SameData SameData SameData
78 // Int Trig No Int No Int No Int No Int No Int No Int No Int
79 // IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
86 // Sngl/CRC Default Default Default Default Default Default Default
87 // WEN# 0 1 1 1 1 1 1 0
88 // REN# 0 0 0 0 0 0 0 0
89 // OE# 0 0 0 0 0 0 0 0
90 // CLRST 0 0 0 0 0 0 0 0
91 // unused 0 0 0 0 0 0 0 0
92 // BOGUS 0 0 0 0 0 0 0 0
97 // GPIF Waveform 2: FIFORd
99 // Interval 0 1 2 3 4 5 6 Idle (7)
100 // _________ _________ _________ _________ _________ _________ _________ _________
102 // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
103 // DataMode NO Data Activate NO Data NO Data NO Data NO Data NO Data
104 // NextData SameData SameData SameData SameData SameData SameData SameData
105 // Int Trig No Int No Int No Int No Int No Int No Int No Int
106 // IF/Wait Wait 1 IF Wait 1 IF Wait 1 Wait 1 Wait 1
107 // Term A TCXpire TCXpire
109 // Term B TCXpire TCXpire
110 // Branch1 Then 2 ThenIdle
111 // Branch0 Else 1 ElseIdle
113 // Sngl/CRC Default Default Default Default Default Default Default
114 // WEN# 0 0 0 0 0 0 0 0
115 // REN# 0 0 0 0 0 0 0 0
116 // OE# 1 1 1 0 0 0 0 0
117 // CLRST 0 0 0 0 0 0 0 0
118 // unused 0 0 0 0 0 0 0 0
119 // BOGUS 0 0 0 0 0 0 0 0
124 // GPIF Waveform 3: FIFOWr
126 // Interval 0 1 2 3 4 5 6 Idle (7)
127 // _________ _________ _________ _________ _________ _________ _________ _________
129 // AddrMode Same Val Same Val Same Val Same Val Same Val Same Val Same Val
130 // DataMode NO Data Activate Activate Activate Activate Activate Activate
131 // NextData SameData SameData SameData SameData SameData SameData SameData
132 // Int Trig No Int No Int No Int No Int No Int No Int No Int
133 // IF/Wait Wait 1 IF Wait 1 Wait 1 Wait 1 Wait 1 Wait 1
140 // Sngl/CRC Default Default Default Default Default Default Default
141 // WEN# 0 0 0 0 0 0 0 0
142 // REN# 0 0 0 0 0 0 0 0
143 // OE# 0 0 0 0 0 0 0 0
144 // CLRST 0 0 0 0 0 0 0 0
145 // unused 0 0 0 0 0 0 0 0
146 // BOGUS 0 0 0 0 0 0 0 0
155 #include "fx2sdly.h" // SYNCDELAY macro
159 const char xdata WaveData[128] =
162 /* LenBr */ 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
163 /* Opcode*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
164 /* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
165 /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
167 /* LenBr */ 0x01, 0x3F, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
168 /* Opcode*/ 0x22, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
169 /* Output*/ 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00,
170 /* LFun */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
172 /* LenBr */ 0x01, 0x11, 0x01, 0x3F, 0x01, 0x01, 0x01, 0x07,
173 /* Opcode*/ 0x00, 0x03, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00,
174 /* Output*/ 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
175 /* LFun */ 0x00, 0x2D, 0x00, 0x2D, 0x00, 0x00, 0x00, 0x3F,
177 /* LenBr */ 0x01, 0x39, 0x01, 0x01, 0x01, 0x01, 0x01, 0x07,
178 /* Opcode*/ 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00,
179 /* Output*/ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
180 /* LFun */ 0x00, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F,
185 const char xdata FlowStates[36] =
187 /* Wave 0 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
188 /* Wave 1 FlowStates */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
189 /* Wave 2 FlowStates */ 0x81,0x2D,0x26,0x00,0x04,0x04,0x03,0x02,0x00,
190 /* Wave 3 FlowStates */ 0x81,0x2D,0x21,0x00,0x04,0x04,0x03,0x02,0x00,
195 const char xdata InitData[7] =
197 /* Regs */ 0xA0,0x00,0x00,0x00,0xEE,0x4E,0x00
201 // TO DO: You may add additional code below.
203 void GpifInit( void )
207 // Registers which require a synchronization delay, see section 15.14
208 // FIFORESET FIFOPINPOLAR
209 // INPKTEND OUTPKTEND
213 // EPxFIFOPFH:L EPxAUTOINLENH:L
214 // EPxFIFOCFG EPxGPIFFLGSEL
215 // PINFLAGSxx EPxFIFOIRQ
218 // UDMACRCH:L EPxGPIFTRIG
221 // Note: The pre-REVE EPxGPIFTCH/L register are affected, as well...
222 // ...these have been replaced by GPIFTC[B3:B0] registers
224 // 8051 doesn't have access to waveform memories 'til
225 // the part is in GPIF mode.
228 // IFCLKSRC=1 , FIFOs executes on internal clk source
229 // xMHz=1 , 48MHz internal clk rate
230 // IFCLKOE=0 , Don't drive IFCLK pin signal at 48MHz
231 // IFCLKPOL=0 , Don't invert IFCLK pin signal from internal clk
232 // ASYNC=1 , master samples asynchronous
233 // GSTATE=1 , Drive GPIF states out on PORTE[2:0], debug WF
234 // IFCFG[1:0]=10, FX2 in GPIF master mode
236 GPIFABORT = 0xFF; // abort any waveforms pending
238 GPIFREADYCFG = InitData[ 0 ];
239 GPIFCTLCFG = InitData[ 1 ];
240 GPIFIDLECS = InitData[ 2 ];
241 GPIFIDLECTL = InitData[ 3 ];
242 GPIFWFSELECT = InitData[ 5 ];
243 GPIFREADYSTAT = InitData[ 6 ];
245 // use dual autopointer feature...
246 AUTOPTRSETUP = 0x07; // inc both pointers,
247 // ...warning: this introduces pdata hole(s)
248 // ...at E67B (XAUTODAT1) and E67C (XAUTODAT2)
251 AUTOPTRH1 = MSB( &WaveData );
252 AUTOPTRL1 = LSB( &WaveData );
259 for ( i = 0x00; i < 128; i++ )
261 EXTAUTODAT2 = EXTAUTODAT1;
264 // Configure GPIF Address pins, output initial value,
265 PORTCCFG = 0xFF; // [7:0] as alt. func. GPIFADR[7:0]
266 OEC = 0xFF; // and as outputs
267 PORTECFG |= 0x80; // [8] as alt. func. GPIFADR[8]
268 OEE |= 0x80; // and as output
270 // ...OR... tri-state GPIFADR[8:0] pins
271 // PORTCCFG = 0x00; // [7:0] as port I/O
272 // OEC = 0x00; // and as inputs
273 // PORTECFG &= 0x7F; // [8] as port I/O
274 // OEE &= 0x7F; // and as input
276 // GPIF address pins update when GPIFADRH/L written
278 GPIFADRH = 0x00; // bits[7:1] always 0
280 GPIFADRL = 0x00; // point to PERIPHERAL address 0x0000
282 // Configure GPIF FlowStates registers for Wave 0 of WaveData
283 FLOWSTATE = FlowStates[ 0 ];
284 FLOWLOGIC = FlowStates[ 1 ];
285 FLOWEQ0CTL = FlowStates[ 2 ];
286 FLOWEQ1CTL = FlowStates[ 3 ];
287 FLOWHOLDOFF = FlowStates[ 4 ];
288 FLOWSTB = FlowStates[ 5 ];
289 FLOWSTBEDGE = FlowStates[ 6 ];
290 FLOWSTBHPERIOD = FlowStates[ 7 ];