3 * Copyright 2004 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
7 * GNU Radio is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * GNU Radio is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with GNU Radio; see the file COPYING. If not, write to
19 * the Free Software Foundation, Inc., 51 Franklin Street,
20 * Boston, MA 02110-1301, USA.
23 #ifndef INCLUDED_USRP_SPI_DEFS_H
24 #define INCLUDED_USRP_SPI_DEFS_H
27 * defines for the VRQ_SPI_READ and VRQ_SPI_WRITE commands
29 * SPI == "Serial Port Interface". SPI is a 3 wire bus plus a
30 * separate enable for each peripheral. The common lines are SCLK,
31 * SDI and SDO. The FX2 always drives SCLK and SDI, the clock and
32 * data lines from the FX2 to the peripheral. When enabled, a
33 * peripheral may drive SDO, the data line from the peripheral to the
36 * The SPI_READ and SPI_WRITE commands are formatted identically.
37 * Each specifies which peripherals to enable, whether the bits should
38 * be transmistted Most Significant Bit first or Least Significant Bit
39 * first, the number of bytes in the optional header, and the number
40 * of bytes to read or write in the body.
42 * The body is limited to 64 bytes. The optional header may contain
43 * 0, 1 or 2 bytes. For an SPI_WRITE, the header bytes are
44 * transmitted to the peripheral followed by the the body bytes. For
45 * an SPI_READ, the header bytes are transmitted to the peripheral,
46 * then len bytes are read back from the peripheral.
50 * SPI_FMT_* goes in wIndexL
52 #define SPI_FMT_xSB_MASK (1 << 7)
53 # define SPI_FMT_LSB (1 << 7) // least signficant bit first
54 # define SPI_FMT_MSB (0 << 7) // most significant bit first
55 #define SPI_FMT_HDR_MASK (3 << 5)
56 # define SPI_FMT_HDR_0 (0 << 5) // 0 header bytes
57 # define SPI_FMT_HDR_1 (1 << 5) // 1 header byte
58 # define SPI_FMT_HDR_2 (2 << 5) // 2 header bytes
61 * SPI_ENABLE_* goes in wIndexH
63 * For the software interface, the enables are active high.
64 * For reads, it's an error to have more than one enable set.
66 * [FWIW, the hardware implements them as active low. Don't change the
67 * definitions of these. They are related to usrp_rev1_regs.h]
69 #define SPI_ENABLE_FPGA 0x01 // select FPGA
70 #define SPI_ENABLE_CODEC_A 0x02 // select AD9862 A
71 #define SPI_ENABLE_CODEC_B 0x04 // select AD9862 B
72 #define SPI_ENABLE_reserved 0x08
73 #define SPI_ENABLE_TX_A 0x10 // select d'board TX A
74 #define SPI_ENABLE_RX_A 0x20 // select d'board RX A
75 #define SPI_ENABLE_TX_B 0x40 // select d'board TX B
76 #define SPI_ENABLE_RX_B 0x80 // select d'board RX B
79 * If there's one header byte, it goes in wValueL.
81 * If there are two header bytes, they go in wValueH | wValueL.
82 * The transmit order of the bytes (and bits within them) is
83 * determined by SPI_FMT_*SB
86 #endif /* INCLUDED_USRP_SPI_DEFS_H */