2 // This file is machine generated from ./fpga_regs_standard.h
3 // Do not edit by hand; your edits will be overwritten.
6 // Register numbers 0 to 31 are reserved for use in fpga_regs_common.h.
7 // Registers 64 to 79 are available for custom FPGA builds.
12 `define FR_INTERP_RATE 7'd32 // [1,1024]
13 `define FR_DECIM_RATE 7'd33 // [1,256]
17 `define FR_RX_FREQ_0 7'd34
18 `define FR_RX_FREQ_1 7'd35
19 `define FR_RX_FREQ_2 7'd36
20 `define FR_RX_FREQ_3 7'd37
22 // See below for DDC Starting Phase
24 // ------------------------------------------------------------------------
25 // configure FPGA Rx mux
28 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
29 // +-----------------------+-------+-------+-------+-------+-+-----+
30 // | must be zero | Q3| I3| Q2| I2| Q1| I1| Q0| I0|Z| NCH |
31 // +-----------------------+-------+-------+-------+-------+-+-----+
33 // There are a maximum of 4 digital downconverters in the the FPGA.
34 // Each DDC has two 16-bit inputs, I and Q, and two 16-bit outputs, I & Q.
36 // DDC I inputs are specified by the two bit fields I3, I2, I1 & I0
38 // 0 = DDC input is from ADC 0
39 // 1 = DDC input is from ADC 1
40 // 2 = DDC input is from ADC 2
41 // 3 = DDC input is from ADC 3
43 // If Z == 1, all DDC Q inputs are set to zero
44 // If Z == 0, DDC Q inputs are specified by the two bit fields Q3, Q2, Q1 & Q0
46 // NCH specifies the number of complex channels that are sent across
47 // the USB. The legal values are 1, 2 or 4, corresponding to 2, 4 or
50 `define FR_RX_MUX 7'd38
52 // ------------------------------------------------------------------------
53 // configure FPGA Tx Mux.
56 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
57 // +-----------------------+-------+-------+-------+-------+-+-----+
58 // | | DAC3 | DAC2 | DAC1 | DAC0 |0| NCH |
59 // +-----------------------------------------------+-------+-+-----+
61 // NCH specifies the number of complex channels that are sent across
62 // the USB. The legal values are 1 or 2, corresponding to 2 or 4
65 // There are two interpolators with complex inputs and outputs.
66 // There are four DACs. (We use the DUC in each AD9862.)
68 // Each 4-bit DACx field specifies the source for the DAC and
69 // whether or not that DAC is enabled. Each subfield is coded
77 // Where E is set if the DAC is enabled, and N specifies which
78 // interpolator output is connected to this DAC.
80 // N which interp output
81 // --- -------------------
87 `define FR_TX_MUX 7'd39
89 // ------------------------------------------------------------------------
92 // Control whether a reference clock is sent to the daughterboards,
93 // and what frequency. The refclk is sent on d'board i/o pin 0.
96 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
97 // +-----------------------------------------------+-+------------+
98 // | Reserved (Must be zero) |E| DIVISOR |
99 // +-----------------------------------------------+-+------------+
102 // Bit 7 -- 1 turns on refclk, 0 allows IO use
103 // Bits 6:0 Divider value
105 `define FR_TX_A_REFCLK 7'd40
106 `define FR_RX_A_REFCLK 7'd41
107 `define FR_TX_B_REFCLK 7'd42
108 `define FR_RX_B_REFCLK 7'd43
111 // ------------------------------------------------------------------------
112 // DDC Starting Phase
114 `define FR_RX_PHASE_0 7'd44
115 `define FR_RX_PHASE_1 7'd45
116 `define FR_RX_PHASE_2 7'd46
117 `define FR_RX_PHASE_3 7'd47
119 // ------------------------------------------------------------------------
120 // Tx data format control register
123 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
124 // +-------------------------------------------------------+-------+
125 // | Reserved (Must be zero) | FMT |
126 // +-------------------------------------------------------+-------+
130 `define FR_TX_FORMAT 7'd48
132 // ------------------------------------------------------------------------
133 // Rx data format control register
136 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
137 // +-----------------------------------------+-+-+---------+-------+
138 // | Reserved (Must be zero) |B|Q| WIDTH | SHIFT |
139 // +-----------------------------------------+-+-+---------+-------+
143 `define FR_RX_FORMAT 7'd49
146 // The valid combinations currently are:
153 // Possible future values of WIDTH = {4, 2, 1}
154 // 12 takes a bit more work, since we need to know packet alignment.
156 // ------------------------------------------------------------------------
157 // FIXME register numbers 50 to 63 are available
159 // ------------------------------------------------------------------------
160 // Registers 64 to 95 are reserved for user custom FPGA builds.
161 // The standard USRP software will not touch these.
163 `define FR_USER_0 7'd64
164 `define FR_USER_1 7'd65
165 `define FR_USER_2 7'd66
166 `define FR_USER_3 7'd67
167 `define FR_USER_4 7'd68
168 `define FR_USER_5 7'd69
169 `define FR_USER_6 7'd70
170 `define FR_USER_7 7'd71
171 `define FR_USER_8 7'd72
172 `define FR_USER_9 7'd73
173 `define FR_USER_10 7'd74
174 `define FR_USER_11 7'd75
175 `define FR_USER_12 7'd76
176 `define FR_USER_13 7'd77
177 `define FR_USER_14 7'd78
178 `define FR_USER_15 7'd79
179 `define FR_USER_16 7'd80
180 `define FR_USER_17 7'd81
181 `define FR_USER_18 7'd82
182 `define FR_USER_19 7'd83
183 `define FR_USER_20 7'd84
184 `define FR_USER_21 7'd85
185 `define FR_USER_22 7'd86
186 `define FR_USER_23 7'd87
187 `define FR_USER_24 7'd88
188 `define FR_USER_25 7'd89
189 `define FR_USER_26 7'd90
190 `define FR_USER_27 7'd91
191 `define FR_USER_28 7'd92
192 `define FR_USER_29 7'd93
193 `define FR_USER_30 7'd94
194 `define FR_USER_31 7'd95
196 //Registers needed for multi usrp master/slave configuration
198 //Rx Master/slave control register (FR_RX_MASTER_SLAVE = FR_USER_0)
200 `define FR_RX_MASTER_SLAVE 7'd64
201 `define bitnoFR_RX_SYNC 0
202 `define bitnoFR_RX_SYNC_MASTER 1
203 `define bitnoFR_RX_SYNC_SLAVE 2
206 //Caution The master settings will output values on the io lines.
207 //They inheritely enable these lines as output. If you have a daughtercard which uses these lines also as output then you will burn your usrp and daughtercard.
208 //If you set the slave bits then your usrp won't do anything if you don't connect a master.
209 // Rx Master/slave control register
211 // The way this is supposed to be used is connecting a (short) 16pin flatcable from an rx daughterboard in RXA master io_rx[8..15] to slave io_rx[8..15] on RXA of slave usrp
212 // This can be done with basic_rx boards or dbsrx boards
213 //dbsrx: connect master-J25 to slave-J25
214 //basic rx: connect J25 to slave-J25
215 //CAUTION: pay attention to the lineup of your connector.
216 //The red line (pin1) should be at the same side of the daughterboards on master and slave.
217 //If you turnaround the cable on one end you will burn your usrp.
219 //You cannot use a 16pin flatcable if you are using FLEX400 or FLEX2400 daughterboards, since these use a lot of the io pins.
220 //You can still link them but you must use only a 2pin or 1pin cable
221 //You can also use a 2-wire link. put a 2pin header on io[15],gnd of the master RXA daughterboard and connect it to io15,gnd of the slave RXA db.
222 //You can use a cable like the ones found with the leds on the mainbord of a PC.
223 //Make sure you don't twist the cable, otherwise you connect the sync output to ground.
224 //To be save you could also just use a single wire from master io[15] to slave io[15], but this is not optimal for signal integrity.
227 // Since rx_io[0] can normally be used as a refclk and is not exported on all daughterboards this line
228 // still has the refclk function if you use the master/slave setup (it is not touched by the master/slave settings).
229 // The master/slave circuitry will only use io pin 15 and does not touch any of the other io pins.
230 `define bitnoFR_RX_SYNC_INPUT_IOPIN 15
231 `define bmFR_RX_SYNC_INPUT_IOPIN (1<<bitnoFR_RX_SYNC_INPUT_IOPIN)
232 //TODO the output pin is still hardcoded in the verilog code, make it listen to the following define
233 `define bitnoFR_RX_SYNC_OUTPUT_IOPIN 15
234 `define bmFR_RX_SYNC_OUTPUT_IOPIN (1<<bitnoFR_RX_SYNC_OUTPUT_IOPIN)
235 // =======================================================================
236 // READBACK Registers
237 // =======================================================================
239 `define FR_RB_IO_RX_A_IO_TX_A 7'd1 // read back a-side i/o pins
240 `define FR_RB_IO_RX_B_IO_TX_B 7'd2 // read back b-side i/o pins
242 // ------------------------------------------------------------------------
243 // FPGA Capability register
246 // 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
247 // +-----------------------------------------------+-+-----+-+-----+
248 // | Reserved (Must be zero) |T|NDUC |R|NDDC |
249 // +-----------------------------------------------+-+-----+-+-----+
251 // Bottom 4-bits are Rx capabilities
252 // Next 4-bits are Tx capabilities
254 `define FR_RB_CAPS 7'd3