2 // This file is machine generated from fpga_regs_common.h
3 // Do not edit by hand; your edits will be overwritten.
6 // This file defines registers common to all FPGA configurations.
7 // Registers 0 to 31 are reserved for use in this file.
10 // The FPGA needs to know the rate that samples are coming from and
11 // going to the A/D's and D/A's. div = 128e6 / sample_rate
13 `define FR_TX_SAMPLE_RATE_DIV 7'd0
14 `define FR_RX_SAMPLE_RATE_DIV 7'd1
19 `define FR_MASTER_CTRL 7'd4 // master enable and reset controls
21 // i/o direction registers for pins that go to daughterboards.
22 // Setting the bit makes it an output from the FPGA to the d'board.
23 // top 16 is mask, low 16 is value
25 `define FR_OE_0 7'd5 // slot 0
30 // i/o registers for pins that go to daughterboards.
31 // top 16 is a mask, low 16 is value
33 `define FR_IO_0 7'd9 // slot 0
41 // If the corresponding bit is set, internal FPGA debug circuitry
42 // controls the i/o pins for the associated bank of daughterboard
43 // i/o pins. Typically used for debugging FPGA designs.
45 `define FR_DEBUG_EN 7'd14
48 // If the corresponding bit is set, enable the automatic DC
49 // offset correction control loop.
51 // The 4 low bits are significant:
58 // This control loop works if the attached daugherboard blocks DC.
59 // Currently all daughterboards do block DC. This includes:
60 // basic rx, dbs_rx, tv_rx, flex_xxx_rx.
62 `define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable
65 // offset corrections for ADC's and DAC's (2's complement)
67 `define FR_ADC_OFFSET_0 7'd16
68 `define FR_ADC_OFFSET_1 7'd17
69 `define FR_ADC_OFFSET_2 7'd18
70 `define FR_ADC_OFFSET_3 7'd19
73 // ------------------------------------------------------------------------
74 // Automatic Transmit/Receive switching
76 // If automatic transmit/receive (ATR) switching is enabled in the
77 // FR_ATR_CTL register, the presence or absence of data in the FPGA
78 // transmit fifo selects between two sets of values for each of the 4
79 // banks of daughterboard i/o pins.
81 // Each daughterboard slot has 3 16-bit registers associated with it:
82 // FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
84 // FR_ATR_MASK_{0,1,2,3}:
86 // These registers determine which of the daugherboard i/o pins are
87 // affected by ATR switching. If a bit in the mask is set, the
88 // corresponding i/o bit is controlled by ATR, else it's output
89 // value comes from the normal i/o pin output register:
92 // FR_ATR_TXVAL_{0,1,2,3}:
93 // FR_ATR_RXVAL_{0,1,2,3}:
95 // If the Tx fifo contains data, then the bits from TXVAL that are
96 // selected by MASK are output. Otherwise, the bits from RXVAL that
97 // are selected by MASK are output.
99 `define FR_ATR_MASK_0 7'd20 // slot 0
100 `define FR_ATR_TXVAL_0 7'd21
101 `define FR_ATR_RXVAL_0 7'd22
103 `define FR_ATR_MASK_1 7'd23 // slot 1
104 `define FR_ATR_TXVAL_1 7'd24
105 `define FR_ATR_RXVAL_1 7'd25
107 `define FR_ATR_MASK_2 7'd26 // slot 2
108 `define FR_ATR_TXVAL_2 7'd27
109 `define FR_ATR_RXVAL_2 7'd28
111 `define FR_ATR_MASK_3 7'd29 // slot 3
112 `define FR_ATR_TXVAL_3 7'd30
113 `define FR_ATR_RXVAL_3 7'd31