2 // This file is machine generated from ./fpga_regs_common.h
3 // Do not edit by hand; your edits will be overwritten.
6 // This file defines registers common to all FPGA configurations.
7 // Registers 0 to 31 are reserved for use in this file.
10 // The FPGA needs to know the rate that samples are coming from and
11 // going to the A/D's and D/A's. div = 128e6 / sample_rate
13 `define FR_TX_SAMPLE_RATE_DIV 7'd0
14 `define FR_RX_SAMPLE_RATE_DIV 7'd1
16 // 2 and 3 are defined in the ATR section
18 `define FR_MASTER_CTRL 7'd4 // master enable and reset controls
20 // i/o direction registers for pins that go to daughterboards.
21 // Setting the bit makes it an output from the FPGA to the d'board.
22 // top 16 is mask, low 16 is value
24 `define FR_OE_0 7'd5 // slot 0
29 // i/o registers for pins that go to daughterboards.
30 // top 16 is a mask, low 16 is value
32 `define FR_IO_0 7'd9 // slot 0
40 // If the corresponding bit is set, internal FPGA debug circuitry
41 // controls the i/o pins for the associated bank of daughterboard
42 // i/o pins. Typically used for debugging FPGA designs.
44 `define FR_DEBUG_EN 7'd14
47 // If the corresponding bit is set, enable the automatic DC
48 // offset correction control loop.
50 // The 4 low bits are significant:
57 // This control loop works if the attached daugherboard blocks DC.
58 // Currently all daughterboards do block DC. This includes:
59 // basic rx, dbs_rx, tv_rx, flex_xxx_rx.
61 `define FR_DC_OFFSET_CL_EN 7'd15 // DC Offset Control Loop Enable
64 // offset corrections for ADC's and DAC's (2's complement)
66 `define FR_ADC_OFFSET_0 7'd16
67 `define FR_ADC_OFFSET_1 7'd17
68 `define FR_ADC_OFFSET_2 7'd18
69 `define FR_ADC_OFFSET_3 7'd19
72 // ------------------------------------------------------------------------
73 // Automatic Transmit/Receive switching
75 // If automatic transmit/receive (ATR) switching is enabled in the
76 // FR_ATR_CTL register, the presence or absence of data in the FPGA
77 // transmit fifo selects between two sets of values for each of the 4
78 // banks of daughterboard i/o pins.
80 // Each daughterboard slot has 3 16-bit registers associated with it:
81 // FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
83 // FR_ATR_MASK_{0,1,2,3}:
85 // These registers determine which of the daugherboard i/o pins are
86 // affected by ATR switching. If a bit in the mask is set, the
87 // corresponding i/o bit is controlled by ATR, else it's output
88 // value comes from the normal i/o pin output register:
91 // FR_ATR_TXVAL_{0,1,2,3}:
92 // FR_ATR_RXVAL_{0,1,2,3}:
94 // If the Tx fifo contains data, then the bits from TXVAL that are
95 // selected by MASK are output. Otherwise, the bits from RXVAL that
96 // are selected by MASK are output.
98 `define FR_ATR_MASK_0 7'd20 // slot 0
99 `define FR_ATR_TXVAL_0 7'd21
100 `define FR_ATR_RXVAL_0 7'd22
102 `define FR_ATR_MASK_1 7'd23 // slot 1
103 `define FR_ATR_TXVAL_1 7'd24
104 `define FR_ATR_RXVAL_1 7'd25
106 `define FR_ATR_MASK_2 7'd26 // slot 2
107 `define FR_ATR_TXVAL_2 7'd27
108 `define FR_ATR_RXVAL_2 7'd28
110 `define FR_ATR_MASK_3 7'd29 // slot 3
111 `define FR_ATR_TXVAL_3 7'd30
112 `define FR_ATR_RXVAL_3 7'd31
114 // Clock ticks to delay rising and falling edge of T/R signal
115 `define FR_ATR_TX_DELAY 7'd2
116 `define FR_ATR_RX_DELAY 7'd3