3 * Copyright 2003,2004 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
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22 #ifndef INCLUDED_FPGA_REGS_COMMON_H
23 #define INCLUDED_FPGA_REGS_COMMON_H
25 // This file defines registers common to all FPGA configurations.
26 // Registers 0 to 31 are reserved for use in this file.
29 // The FPGA needs to know the rate that samples are coming from and
30 // going to the A/D's and D/A's. div = 128e6 / sample_rate
32 #define FR_TX_SAMPLE_RATE_DIV 0
33 #define FR_RX_SAMPLE_RATE_DIV 1
35 // 2 and 3 are defined in the ATR section
37 #define FR_MASTER_CTRL 4 // master enable and reset controls
38 # define bmFR_MC_ENABLE_TX (1 << 0)
39 # define bmFR_MC_ENABLE_RX (1 << 1)
40 # define bmFR_MC_RESET_TX (1 << 2)
41 # define bmFR_MC_RESET_RX (1 << 3)
43 // i/o direction registers for pins that go to daughterboards.
44 // Setting the bit makes it an output from the FPGA to the d'board.
45 // top 16 is mask, low 16 is value
47 #define FR_OE_0 5 // slot 0
52 // i/o registers for pins that go to daughterboards.
53 // top 16 is a mask, low 16 is value
55 #define FR_IO_0 9 // slot 0
61 # define bmFR_MODE_NORMAL 0
62 # define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback
63 # define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting
64 # define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter
65 // low and high 16 bits are multiplexed across channel I and Q
68 // If the corresponding bit is set, internal FPGA debug circuitry
69 // controls the i/o pins for the associated bank of daughterboard
70 // i/o pins. Typically used for debugging FPGA designs.
72 #define FR_DEBUG_EN 14
73 # define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
74 # define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
75 # define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
76 # define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
79 // If the corresponding bit is set, enable the automatic DC
80 // offset correction control loop.
82 // The 4 low bits are significant:
89 // This control loop works if the attached daugherboard blocks DC.
90 // Currently all daughterboards do block DC. This includes:
91 // basic rx, dbs_rx, tv_rx, flex_xxx_rx.
93 #define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable
96 // offset corrections for ADC's and DAC's (2's complement)
98 #define FR_ADC_OFFSET_0 16
99 #define FR_ADC_OFFSET_1 17
100 #define FR_ADC_OFFSET_2 18
101 #define FR_ADC_OFFSET_3 19
104 // ------------------------------------------------------------------------
105 // Automatic Transmit/Receive switching
107 // If automatic transmit/receive (ATR) switching is enabled in the
108 // FR_ATR_CTL register, the presence or absence of data in the FPGA
109 // transmit fifo selects between two sets of values for each of the 4
110 // banks of daughterboard i/o pins.
112 // Each daughterboard slot has 3 16-bit registers associated with it:
113 // FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
115 // FR_ATR_MASK_{0,1,2,3}:
117 // These registers determine which of the daugherboard i/o pins are
118 // affected by ATR switching. If a bit in the mask is set, the
119 // corresponding i/o bit is controlled by ATR, else it's output
120 // value comes from the normal i/o pin output register:
123 // FR_ATR_TXVAL_{0,1,2,3}:
124 // FR_ATR_RXVAL_{0,1,2,3}:
126 // If the Tx fifo contains data, then the bits from TXVAL that are
127 // selected by MASK are output. Otherwise, the bits from RXVAL that
128 // are selected by MASK are output.
130 #define FR_ATR_MASK_0 20 // slot 0
131 #define FR_ATR_TXVAL_0 21
132 #define FR_ATR_RXVAL_0 22
134 #define FR_ATR_MASK_1 23 // slot 1
135 #define FR_ATR_TXVAL_1 24
136 #define FR_ATR_RXVAL_1 25
138 #define FR_ATR_MASK_2 26 // slot 2
139 #define FR_ATR_TXVAL_2 27
140 #define FR_ATR_RXVAL_2 28
142 #define FR_ATR_MASK_3 29 // slot 3
143 #define FR_ATR_TXVAL_3 30
144 #define FR_ATR_RXVAL_3 31
146 // Clock ticks to delay rising and falling edge of T/R signal
147 #define FR_ATR_TX_DELAY 2
148 #define FR_ATR_RX_DELAY 3
150 #endif /* INCLUDED_FPGA_REGS_COMMON_H */