3 * Copyright 2003,2004 Free Software Foundation, Inc.
5 * This file is part of GNU Radio
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8 * it under the terms of the GNU General Public License as published by
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
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22 #ifndef INCLUDED_FPGA_REGS_COMMON_H
23 #define INCLUDED_FPGA_REGS_COMMON_H
25 // This file defines registers common to all FPGA configurations.
26 // Registers 0 to 31 are reserved for use in this file.
29 // The FPGA needs to know the rate that samples are coming from and
30 // going to the A/D's and D/A's. div = 128e6 / sample_rate
32 #define FR_TX_SAMPLE_RATE_DIV 0
33 #define FR_RX_SAMPLE_RATE_DIV 1
38 #define FR_MASTER_CTRL 4 // master enable and reset controls
39 # define bmFR_MC_ENABLE_TX (1 << 0)
40 # define bmFR_MC_ENABLE_RX (1 << 1)
41 # define bmFR_MC_RESET_TX (1 << 2)
42 # define bmFR_MC_RESET_RX (1 << 3)
44 // i/o direction registers for pins that go to daughterboards.
45 // Setting the bit makes it an output from the FPGA to the d'board.
46 // top 16 is mask, low 16 is value
48 #define FR_OE_0 5 // slot 0
53 // i/o registers for pins that go to daughterboards.
54 // top 16 is a mask, low 16 is value
56 #define FR_IO_0 9 // slot 0
62 # define bmFR_MODE_NORMAL 0
63 # define bmFR_MODE_LOOPBACK (1 << 0) // enable digital loopback
64 # define bmFR_MODE_RX_COUNTING (1 << 1) // Rx is counting
65 # define bmFR_MODE_RX_COUNTING_32BIT (1 << 2) // Rx is counting with a 32 bit counter
66 // low and high 16 bits are multiplexed across channel I and Q
69 // If the corresponding bit is set, internal FPGA debug circuitry
70 // controls the i/o pins for the associated bank of daughterboard
71 // i/o pins. Typically used for debugging FPGA designs.
73 #define FR_DEBUG_EN 14
74 # define bmFR_DEBUG_EN_TX_A (1 << 0) // debug controls TX_A i/o
75 # define bmFR_DEBUG_EN_RX_A (1 << 1) // debug controls RX_A i/o
76 # define bmFR_DEBUG_EN_TX_B (1 << 2) // debug controls TX_B i/o
77 # define bmFR_DEBUG_EN_RX_B (1 << 3) // debug controls RX_B i/o
80 // If the corresponding bit is set, enable the automatic DC
81 // offset correction control loop.
83 // The 4 low bits are significant:
90 // This control loop works if the attached daugherboard blocks DC.
91 // Currently all daughterboards do block DC. This includes:
92 // basic rx, dbs_rx, tv_rx, flex_xxx_rx.
94 #define FR_DC_OFFSET_CL_EN 15 // DC Offset Control Loop Enable
97 // offset corrections for ADC's and DAC's (2's complement)
99 #define FR_ADC_OFFSET_0 16
100 #define FR_ADC_OFFSET_1 17
101 #define FR_ADC_OFFSET_2 18
102 #define FR_ADC_OFFSET_3 19
105 // ------------------------------------------------------------------------
106 // Automatic Transmit/Receive switching
108 // If automatic transmit/receive (ATR) switching is enabled in the
109 // FR_ATR_CTL register, the presence or absence of data in the FPGA
110 // transmit fifo selects between two sets of values for each of the 4
111 // banks of daughterboard i/o pins.
113 // Each daughterboard slot has 3 16-bit registers associated with it:
114 // FR_ATR_MASK_*, FR_ATR_TXVAL_* and FR_ATR_RXVAL_*
116 // FR_ATR_MASK_{0,1,2,3}:
118 // These registers determine which of the daugherboard i/o pins are
119 // affected by ATR switching. If a bit in the mask is set, the
120 // corresponding i/o bit is controlled by ATR, else it's output
121 // value comes from the normal i/o pin output register:
124 // FR_ATR_TXVAL_{0,1,2,3}:
125 // FR_ATR_RXVAL_{0,1,2,3}:
127 // If the Tx fifo contains data, then the bits from TXVAL that are
128 // selected by MASK are output. Otherwise, the bits from RXVAL that
129 // are selected by MASK are output.
131 #define FR_ATR_MASK_0 20 // slot 0
132 #define FR_ATR_TXVAL_0 21
133 #define FR_ATR_RXVAL_0 22
135 #define FR_ATR_MASK_1 23 // slot 1
136 #define FR_ATR_TXVAL_1 24
137 #define FR_ATR_RXVAL_1 25
139 #define FR_ATR_MASK_2 26 // slot 2
140 #define FR_ATR_TXVAL_2 27
141 #define FR_ATR_RXVAL_2 28
143 #define FR_ATR_MASK_3 29 // slot 3
144 #define FR_ATR_TXVAL_3 30
145 #define FR_ATR_RXVAL_3 31
147 #endif /* INCLUDED_FPGA_REGS_COMMON_H */