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8 <title>USRP User's and Developer's Guide</title>
10 <firstname>Matt</firstname>
11 <surname>Ettus</surname>
13 <orgname>Ettus Research LLC</orgname>
16 <street>604 Mariposa Ave</street>
17 <city>Mountain View</city>, <state>CA</state> <postcode>94041</postcode>
18 <country>USA</country>
19 <email>matt@ettus.com</email>
26 This guide explains both basic usage of the USRP as well as how to expand it.
33 <title>Introduction</title>
35 The Universal Software Radio Peripheral, or USRP (pronounced "usurp")
36 is designed to allow general purpose computers to function as high
37 bandwidth software radios. In essence, it serves as a digital
38 baseband and IF section of a radio communication system. In addition,
39 it has a well-defined electrical and mechanical interface to RF
40 front-ends (daughterboards) which can translate between that IF or
41 baseband and the RF bands of interest
44 The basic design philosophy behind the USRP has been to do all of the
45 waveform-specific processing, like modulation and demodulation, on the
46 host CPU. All of the high-speed general purpose operations like
47 digital up- and downconversion, decimation and interpolation are done
51 It is anticipated that the majority of USRP users will never need to
52 use anything other than the standard FPGA configuration. However, for
53 those users that wish to, the FPGA design may be changed or replaced.
54 All of the interfaces are well defined and documented.
56 <figure id="usrp-board">
57 <title>USRP with Daughterboards</title>
59 <imageobject><imagedata fileref="usrp.jpg" format="JPG"/></imageobject>
61 This USRP has 2 BasicTX and 2 BasicRX boards mounted on it.
62 Notice that the boards on the left are rotated 180 degrees.
67 <sect2 id="requirements">
68 <title>System Requirements</title>
70 The USRP requires a PC or Mac with a USB2 interface.
74 <sect2 id="capabilities">
75 <title>Capabilities</title>
77 The USRP has 4 high-speed analog to digital converters (ADCs), each at
78 12 bits per sample, 64 million samples per second. There are also
79 4 high-speed digital to analog converters (DACs), each at 14 bits per
80 sample, 128 million samples per second. These 4 input and 4 output
81 channels are connected to an Altera Cyclone EP1C12 FPGA. The FPGA, in
82 turn, connects to a USB2 interface chip, the Cypress FX2, and on to the
83 computer. The USRP connects to the computer via a high speed USB2
84 interface only, and will not work with USB1.1.
86 <figure id="usrp-block-diagram-fig"><title>Universal Software Radio Peripheral</title>
88 <imageobject><imagedata fileref="usrp-block-diagram.eps" format="EPS"/></imageobject>
89 <imageobject><imagedata fileref="usrp-block-diagram.png" format="PNG"/></imageobject>
90 <caption><para></para></caption>
95 <sect1 id="getting-started">
96 <title>Getting Started</title>
98 <title>Getting all the Software</title>
100 The first step in using your USRP system is to get all of GNU Radio installed. This can
101 sometimes be a daunting process, as there are several other libraries which will need to be
104 <sect3 id="dependencies">
105 <title>Library Dependencies</title>
110 We use SWIG (Simple Wrapper Interface Generator) to tie together the C++ and Python code
111 in the GNU Radio system. We require that you have version 1.3.24 or newer. You'll
112 probably have to compile it from source, which you can find here: <ulink url="http://www.swig.org">SWIG</ulink>
118 FFTW is the library which GNU Radio uses for FFTs. GNU Radio requires version 3.0.1 or
119 newer, and it must be compiled for single precision. You can get it from the
120 <ulink url="http://www.fftw.org">FFTW Homepage</ulink>
124 <para>Boost Library</para>
126 Boost provides several low-level structures used in our C++ code. If it is not included in
127 your OS distribution, you can get it here: <ulink url="http://boost.org">Boost</ulink>
131 <para>CPP Unit</para>
133 CPPUnit provides our unit-testing framework. This creates automated tests to insure that
134 code does not break when changes are made. Get it at the <ulink url="http://cppunit.sf.net">
135 CPP Unit Homepage</ulink>
140 <sect3 id="getting-gradio">
141 <title>Getting GNU Radio and the USRP code</title>
143 There are several packages of software which make up GNU Radio and the USRP support software.
144 Links to the latest versions of each can be found on the GNU Radio Wiki at
145 <ulink url="http://comsec.com/wiki?GnuRadio2.X">Download Links</ulink>. Gr-build
146 can greatly simplify the installation process, and its use it highly recommended.
150 <title>Following CVS Development</title>
152 Development for the USRP proceeds very quickly at times, so some users may want to keep up with
153 the latest by following the CVS trees. There are three separate software repositories
154 which contain various parts of the USRP system.
158 USRP-HW, containing the hardware and FPGA designs.
161 All of the schematics in this repository were created in
162 <ulink url="http://www.geda.seul.org">gEDA</ulink>. The board
163 layouts were created in <ulink url="http://pcb.sf.net">PCB</ulink>.
164 Verilog designs are compiled in Quartus II Web Edition from
165 <ulink url="http://www.altera.com">Altera</ulink>.
170 <ulink url="https://sourceforge.net/cvs/?group_id=22397">USRP-SW</ulink>,
171 USRP-SW, containing firmware and host drivers for the USRP
174 Host side drivers and firmware which runs in the USB2 interface chip on the board.
179 <ulink url="http://comsec.com/wiki?CvsAccess">GNU Radio/gr-usrp</ulink>
180 which contains the GNU Radio interface to the USRP
187 <sect2 id="usrp-start">
188 <title>Using your USRP</title>
189 <sect3 id="physical">
190 <title>Mechanical Connection</title>
192 The USRP ships with a complete set of standoffs, nuts and bolts. There are 20 standoffs,
193 M3x10mm M-F, of which 4 are intended to be used as "feet" for the USRP. Place them in the 4
194 corner holes on the main board, inserting the male part from below. The remaining 16
195 are used to hold the daughterboards in place. Four of them should be connected to the male
196 portion of the 4 standoffs already inserted from below. The remaining 12 should be
197 connected to the board with the 12 M3x6mm screws from below. At this point there should be
198 16 standoffs on the board with the male ends up to serve as a guide for the daughterboards.
199 The 16 M3 nuts are used to fasten the daughterboards down to the main board.
202 The USRP accomodates 2 TX and 2 RX daughterboards. The placement of the standoffs is designed
203 to prevent the accidental incorrect connection of daughterboards. The 2 sides of the USRP have
204 their daughterboard slots rotated 180 degrees. The USRP should not be operated without
205 standoffs, and daughterboards should never be connected or removed while power is applied.
208 <sect3 id="electrical">
209 <title>Electrical Connections</title>
211 The USRP is powered by a 6V 4A power converter included in the kit. The converter is
212 capable of 90-260 Vac, 50/60 Hz operation, and so should work in any country.
213 If there is a need to use another power supply, the connector is a standard 2.1mm/5.5mm
214 DC power connector. The USRP itself only needs 5V at 2A, but a 6V supply was chosen to
215 accomodate future daughterboards. Extra power supplies are available from Ettus Research.
218 The included USB cable should be connected to a USB2-capable socket on a computer. The USRP
219 does not support USB 1.1 operation at this time.
222 <sect3 id="diagnostics">
223 <title>Troubleshooting</title>
225 When first powered up, an LED on the USRP should be flashing at about 3-4x per second.
226 This indicates that the processor is running, and has put the device in a low power mode.
227 Once firmware has been downloaded to the USRP, the LED will blink at a slower rate.
228 If there is no blinking LED, check all power connections, and check for continuity
229 in the power fuse (F501, near the power connector). If the fuse needs replacement, it
230 is size 0603, 3 amps.
237 <sect2 id="fpga-std">
238 <title>Standard FPGA Configuration</title>
240 In the standard fpga configuration, usrp_std, all samples sent over
241 the USB interface are in 16-bit signed integers in IQ format. When
242 there are multiple channels (up to 4), the channels are interleaved.
243 For example, with 4 channels, the sequence would be I0 Q0 I1 Q1 I2 Q2
247 The USRP can operate in full duplex mode. When in this mode, the
248 transmit and receive sides are completely independent of one another.
249 The only consideration is that the combined data rate over the bus
250 must be 32 Megabytes per second or less. The multiple RX channels
251 (1,2, or 4) must all be the same data rate (i.e. same decimation
252 ratio). The same applies to the 1,2, or TX channels, which each must
253 be at the same data rate (which may be different from the RX rate).
256 On the RX side, each of the 4 ADCs can be routed to either of I or the
257 Q input of any of the 4 downconverters. This allows for having
258 multiple channels selected out of the same ADC sample stream.
261 The digital upconverters (DUCs) on the transmit side are actually
262 contained in the AD9862 CODEC chips, not in the FPGA. The only
263 transmit signal processing blocks in the FPGA are the interpolators.
264 The interpolator outputs can be routed to any of the 4 CODEC inputs.
266 <figure id="ddc-fig"><title>Digital Down Converter Block Diagram</title>
268 <imageobject><imagedata fileref="ddc.eps" format="EPS"/></imageobject>
269 <imageobject><imagedata fileref="ddc.png" format="PNG"/></imageobject>
270 <caption><para></para></caption>
276 <sect1 id="dboard-int">
277 <title>Daughterboard Interface</title>
278 <sect2 id="power-int">
281 Daughterboards are provided with clean regulated 3.3V for the analog
282 and digital sections. Additionally there is a 6V connection straight from
283 the wall supply which is intended to supply a 5V LDO regulator. All daughterboards
284 may draw a combined total of 1.5 A.
287 <sect2 id="logical-int">
288 <title>Logical Interface</title>
290 There are slots for 2 TX daughterboards, labeled TXA and TXB, and 2
291 corresponding RX daughterboards, RXA and RXB. Each daughterboard slot has
292 access to 2 of the 4 high-speed data converter analog signals (DAC outputs
293 for TX, ADC inputs for RX). This allows each daughterboard which uses real
294 (not IQ) sampling to have 2 independent RF sections, and 2 antennas
295 (4 total for the system). If IQ sampling is used, each board can support
296 a single RF section, for a total of 2 for the whole system.
299 No antialias or reconstruction filtering is provided on the USRP motherboard.
300 This allows for maximum flexibility in frequency planning for the
301 daughterboards. The analog input bandwidth of the ADCs is over 200 MHz, so
302 IF frequencies up to that high may be chosen. If several decibels of loss
303 is tolerable, and IF frequency as high as 500 MHz can be used.
306 Every daughterboard has an I2C EEPROM (24LC024 or 24LC025) onboard
307 which identifies the board to the system. This allows the host
308 software to automatically set up the system properly based on the
309 installed daughterboard. The EEPROM may also store calibration values
310 like DC offsets or IQ imbalances. If this EEPROM is not programmed, a
311 warning message is printed every time USRP software is run.
314 <sect2 id="analog-int">
315 <title>Analog Interface</title>
317 Each RX daughterboard has 2 differential analog inputs
318 (VINP_A/VINN_A and VINP_B/VINN_B) which are sampled at a rate of 64 MS/s.
319 The input impedance is approximately 1Kohm.
320 The motherboard has a software-controllable programmable gain amplifier
321 on these inputs, with 0 to 20 dB of gain. With gain set to zero, full
322 scale inputs are 2 Volts peak-to-peak differential. When set to 20 dB,
323 only .2 V pk-pk differential is needed to reach full scale.
326 If signals are AC-coupled, there is no need to provide DC bias as long as the
327 internal buffer is turned on. It will provide an approximately 2V bias.
328 If signals are DC-couple, a DC bias of Vdd/2 (1.65V) should be provided to
329 both the positive and negative inputs, and the internal buffer should be turned off.
330 VREF provides a clean 1 V reference.
333 Each TX daughterboard has a pair of differential analog outputs which are
334 updated at 128 MS/s. The signals (IOUTP_A/IOUTN_A and IOUTP_B/IOUTN_B) are
335 current-output, each varying between 0 and 20 mA. Since they are high-impedance,
336 they can be converted into differential voltages with a resistor.
339 In addition to the high-speed signals, each daughterboard has exclusive access to 2 low-speed ADC inputs
340 (labeled AUX_ADC_A and AUX_ADC_B) which can be read from software.
341 These are useful for sensing RSSI signal levels, temperatures, bias
342 levels, etc. Additionally, each board has shared access to 4 low-speed DAC
343 signals, labeled AUX_DAC_A through AUX_DAC_D. RXA and TXA share one set
344 of these 4 lines, and RXB and TXB share their own independent set. These
345 signals are useful for controlling gain of variable-gain amplifiers, for example.
346 AUX_ADC_REF provides a reference level for gain setting if it is necessary.
351 <title>Digital Interface</title>
354 <sect2 id="mech-int">
355 <title>Connector Pinouts</title>
357 <table frame='all'><title>RX DBoard Connector</title>
358 <tgroup cols='3' align='left' colsep='1' rowsep='1'>
363 <entry>Description</entry>
370 <entry>This is power</entry>
387 <title>Available Daughterboards</title>
389 <title>BasicRX</title>
394 <title>BasicTX</title>