2 # README -- the short version
5 The top level makefile handles the host code and FX2 firmware.
7 Besides the normal gcc suite and all the auto tools, you'll need
8 the SDCC free C compiler to build the firmware. You MUST
9 USE VERSION 2.4.0 or VERSION 2.5.0 due to some problems with variable
10 initialization. http://sdcc.sourceforge.net
15 ./bootstrap # if you're building from CVS
18 make && make check && make install
21 The high level interface to the USRP using our standard FPGA bitstram
22 is contained in usrp/host/lib/usrp_standard.h
24 If you've got doxygen installed, there are html docs in
25 usrp/doc/html/index.html
28 # Compiling the verilog (not required unless you're modifying it)
30 If you want to build the FPGA .rbf file from source (not required; we
31 provide pre-compiled .rbf files in usrp/fpga/rbf directory), you'll
32 need Altera's no cost Quartus II development tools. We're currently
33 building with Quartus II 5.1sp1 Web Edition. The project file is
34 usrp/fpga/toplevel/usrp_std/usrp_std.qpf. The toplevel verilog file
35 is usrp/fpga/toplevel/usrp_std/usrp_std.v. The bulk of the verilog
36 modules are contained in usrp/fpga/sdr_lib