3 <title>Test results for version 1.62</title>
17 <td>Initial state</td>
19 <td>Expected output</td>
20 <td>Actual output</td>
24 <td><a name="CON001"/>CON001</td>
27 <td>Telnet connection</td>
28 <td>Power on, jtag target attached</td>
29 <td>On console, type<br><code>telnet ip port</code></td>
30 <td><code>Open On-Chip Debugger<br>></code></td>
31 <td><code>> telnet 10.0.0.142<br>
32 Trying 10.0.0.142...<br>
33 Connected to 10.0.0.142.<br>
34 Escape character is '^]'.<br>
35 Open On-Chip Debugger<br>
41 <td><a name="CON002"/>CON002</td>
44 <td>GDB server connection</td>
45 <td>Power on, jtag target attached</td>
46 <td>On GDB console, type<br><code>target remote ip:port</code></td>
47 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
49 (gdb) tar remo 10.0.0.142:3333<br>
50 Remote debugging using 10.0.0.142:3333<br>
51 0x00016434 in ?? ()<br>
65 <td>Initial state</td>
67 <td>Expected output</td>
68 <td>Actual output</td>
72 <td><a name="RES001"/>RES001</td>
75 <td>Reset halt on a blank target</td>
76 <td>Erase all the content of the flash</td>
77 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
78 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
83 SRST took 2ms to deassert<br>
84 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
85 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
86 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
87 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
88 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
89 Trying to use configured scan chain anyway...<br>
90 Bypassing JTAG setup events due to errors<br>
91 SRST took 2ms to deassert<br>
92 target state: halted<br>
93 target halted in ARM state due to debug-request, current mode: Supervisor<br>
94 cpsr: 0x000000d3 pc: 0x00000000<br>
95 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
102 <td><a name="RES002"/>RES002</td>
105 <td>Reset init on a blank target</td>
106 <td>Erase all the content of the flash</td>
107 <td>Connect via the telnet interface and type <br><code>reset init</code></td>
108 <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
113 SRST took 2ms to deassert<br>
114 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
115 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
116 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
117 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
118 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
119 Trying to use configured scan chain anyway...<br>
120 Bypassing JTAG setup events due to errors<br>
121 SRST took 2ms to deassert<br>
122 target state: halted<br>
123 target halted in ARM state due to debug-request, current mode: Supervisor<br>
124 cpsr: 0x000000d3 pc: 0x00000000<br>
125 cleared protection for sectors 0 through 7 on flash bank 0<br>
126 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
133 <td><a name="RES003"/>RES003</td>
136 <td>Reset after a power cycle of the target</td>
137 <td>Reset the target then power cycle the target</td>
138 <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
139 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
142 nsed nSRST asserted.<br>
143 nsed power dropout.<br>
144 nsed power restore.<br>
146 SRST took 85ms to deassert<br>
147 SRST took 2ms to deassert<br>
148 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
149 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
150 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
151 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
152 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
153 Trying to use configured scan chain anyway...<br>
154 Bypassing JTAG setup events due to errors<br>
155 SRST took 2ms to deassert<br>
156 target state: halted<br>
157 target halted in ARM state due to debug-request, current mode: Supervisor<br>
158 cpsr: 0x000000d3 pc: 0x00000000<br>
159 cleared protection for sectors 0 through 7 on flash bank 0<br>
160 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
163 SRST took 2ms to deassert<br>
164 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
165 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
166 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
167 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
168 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
169 Trying to use configured scan chain anyway...<br>
170 Bypassing JTAG setup events due to errors<br>
171 SRST took 2ms to deassert<br>
172 target state: halted<br>
173 target halted in ARM state due to debug-request, current mode: Supervisor<br>
174 cpsr: 0x000000d3 pc: 0x00000000<br>
175 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
182 <td><a name="RES004"/>RES004</td>
185 <td>Reset halt on a blank target where reset halt is supported</td>
186 <td>Erase all the content of the flash</td>
187 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
188 <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
193 SRST took 2ms to deassert<br>
194 JTAG tap: str912.flash tap/device found: 0x04570041 (Manufacturer: 0x020, Part: 0x4570, Version: 0x0)<br>
195 JTAG Tap/device matched<br>
196 JTAG tap: str912.cpu tap/device found: 0x25966041 (Manufacturer: 0x020, Part: 0x5966, Version: 0x2)<br>
197 JTAG Tap/device matched<br>
198 JTAG tap: str912.bs tap/device found: 0x2457f041 (Manufacturer: 0x020, Part: 0x457f, Version: 0x2)<br>
199 JTAG Tap/device matched<br>
200 SRST took 2ms to deassert<br>
201 target state: halted<br>
202 target halted in ARM state due to debug-request, current mode: Supervisor<br>
203 cpsr: 0x000000d3 pc: 0x00000000<br>
209 <td><a name="RES005"/>RES005</td>
212 <td>Reset halt on a blank target using return clock</td>
213 <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
214 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
215 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
220 SRST took 2ms to deassert<br>
221 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
222 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
223 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
224 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
225 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
226 Trying to use configured scan chain anyway...<br>
227 Bypassing JTAG setup events due to errors<br>
228 SRST took 2ms to deassert<br>
229 target state: halted<br>
230 target halted in ARM state due to debug-request, current mode: Supervisor<br>
231 cpsr: 0x000000d3 pc: 0x00000000<br>
232 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
247 <td>Initial state</td>
249 <td>Expected output</td>
250 <td>Actual output</td>
254 <td><a name="SPD001"/>SPD001</td>
257 <td>16MHz on normal operation</td>
258 <td>Reset init the target according to RES002 </td>
259 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
260 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
264 jtag_speed 4 => JTAG clk=16.000000<br>
266 ThumbEE -- incomplete support<br>
267 target state: halted<br>
268 target halted in ThumbEE state due to debug-request, current mode: System<br>
269 cpsr: 0xfdfdffff pc: 0xfdfdfff9<br>
271 0x00000000: 00000000 00000000 ffffffff ffffffff 00000001 ffffffff 00000001 ffffffff<br>
272 0x00000020: 00000001 00000001 00000001 00000001 00000001 fffffffe fffffffe 00000001<br>
273 0x00000040: fffffffe 00000000 00000000 00000000 00000000 00000000 00000000 00000000<br>
274 0x00000060: 00000000 00000000 00000000 00000000 ffffffff ffffffff 00000001 00000000<br>
275 invalid mode value encountered 0<br>
276 cpsr contains invalid mode value - communication failure<br>
277 ThumbEE -- incomplete support<br>
278 target state: halted<br>
279 target halted in ThumbEE state due to debug-request, current mode: System<br>
280 cpsr: 0xffffffff pc: 0xfffffff8<br>
284 <td><font color=red><b>FAIL</b></font></td>
287 <td><a name="SPD002"/>SPD002</td>
290 <td>8MHz on normal operation</td>
291 <td>Reset init the target according to RES002 </td>
292 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
293 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
297 jtag_speed 8 => JTAG clk=8.000000<br>
300 invalid mode value encountered 0<br>
301 cpsr contains invalid mode value - communication failure<br>
302 Command handler execution failed<br>
303 in procedure 'halt' called at file "command.c", line 647<br>
304 called at file "command.c", line 361<br>
305 Halt timed out, wake up GDB.<br>
309 <td><font color=red><b>FAIL</b></font></td>
312 <td><a name="SPD003"/>SPD003</td>
315 <td>4MHz on normal operation</td>
316 <td>Reset init the target according to RES002 </td>
317 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
318 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
322 jtag_speed 16 => JTAG clk=4.000000<br>
326 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
327 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
328 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
329 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
336 <td><a name="SPD004"/>SPD004</td>
339 <td>2MHz on normal operation</td>
340 <td>Reset init the target according to RES002 </td>
341 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
342 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
346 jtag_speed 32 => JTAG clk=2.000000<br>
350 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
351 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
352 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
353 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
360 <td><a name="SPD005"/>SPD005</td>
363 <td>RCLK on normal operation</td>
364 <td>Reset init the target according to RES002 </td>
365 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
366 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
373 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
374 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
375 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
376 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
391 <td>Initial state</td>
393 <td>Expected output</td>
394 <td>Actual output</td>
398 <td><a name="DBG001"/>DBG001</td>
401 <td>Load is working</td>
402 <td>Reset init is working, RAM is accesible, GDB server is started</td>
403 <td>On the console of the OS: <br>
404 <code>arm-elf-gdb test_ram.elf</code><br>
405 <code>(gdb) target remote ip:port</code><br>
406 <code>(gdb) load</load>
408 <td>Load should return without error, typical output looks like:<br>
410 Loading section .text, size 0x14c lma 0x0<br>
411 Start address 0x40, load size 332<br>
412 Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
417 Loading section .text, size 0x1a0 lma 0x4000000<br>
418 Loading section .rodata, size 0x4 lma 0x40001a0<br>
419 Start address 0x4000000, load size 420<br>
420 Transfer rate: 29 KB/sec, 210 bytes/write.<br>
427 <td><a name="DBG002"/>DBG002</td>
430 <td>Software breakpoint</td>
431 <td>Load the test_ram.elf application, use instructions from GDB001</td>
432 <td>In the GDB console:<br>
434 (gdb) monitor gdb_breakpoint_override soft<br>
435 force soft breakpoints<br>
437 Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
442 <td>The software breakpoint should be reached, a typical output looks like:<br>
444 target state: halted<br>
445 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
446 cpsr: 0x000000d3 pc: 0x000000ec<br>
448 Breakpoint 1, main () at src/main.c:71<br>
454 (gdb) monitor gdb_breakpoint_override soft<br>
455 force soft breakpoints<br>
456 Current language: auto<br>
457 The current source language is "auto; currently asm".<br>
459 Breakpoint 1 at 0x4000144: file src/main.c, line 69.<br>
463 Breakpoint 1, main () at src/main.c:69<br>
464 warning: Source file is more recent than executable.<br>
466 Current language: auto<br>
467 The current source language is "auto; currently c".<br>
474 <td><a name="DBG003"/>DBG003</td>
477 <td>Single step in a RAM application</td>
478 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
479 <td>In GDB, type <br><code>(gdb) step</code></td>
480 <td>The next instruction should be reached, typical output:<br>
483 target state: halted<br>
484 target halted in ARM state due to single step, current mode: Abort<br>
485 cpsr: 0x20000097 pc: 0x000000f0<br>
486 target state: halted<br>
487 target halted in ARM state due to single step, current mode: Abort<br>
488 cpsr: 0x20000097 pc: 0x000000f4<br>
502 <td><a name="DBG004"/>DBG004</td>
505 <td>Software break points are working after a reset</td>
506 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
507 <td>In GDB, type <br><code>
508 (gdb) monitor reset init<br>
512 <td>The breakpoint should be reached, typical output:<br>
514 target state: halted<br>
515 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
516 cpsr: 0x000000d3 pc: 0x000000ec<br>
518 Breakpoint 1, main () at src/main.c:71<br>
523 (gdb) monitor reset init<br>
525 SRST took 2ms to deassert<br>
526 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
527 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
528 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
529 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
530 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
531 Trying to use configured scan chain anyway...<br>
532 Bypassing JTAG setup events due to errors<br>
533 SRST took 2ms to deassert<br>
534 target state: halted<br>
535 target halted in ARM state due to debug-request, current mode: Supervisor<br>
536 cpsr: 0x000000d3 pc: 0x00000000<br>
537 cleared protection for sectors 0 through 7 on flash bank 0<br>
538 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
540 Loading section .text, size 0x1a0 lma 0x4000000<br>
541 Loading section .rodata, size 0x4 lma 0x40001a0<br>
542 Start address 0x4000000, load size 420<br>
543 Transfer rate: 25 KB/sec, 210 bytes/write.<br>
547 Breakpoint 1, main () at src/main.c:69<br>
554 <td><a name="DBG005"/>DBG005</td>
557 <td>Hardware breakpoint</td>
558 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
559 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
561 (gdb) monitor reset init<br>
563 Loading section .text, size 0x194 lma 0x100000<br>
564 Start address 0x100040, load size 404<br>
565 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
566 (gdb) monitor gdb_breakpoint_override hard<br>
567 force hard breakpoints<br>
569 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
573 <td>The breakpoint should be reached, typical output:<br>
577 Breakpoint 1, main () at src/main.c:69<br>
583 (gdb) monitor reset init<br>
585 SRST took 2ms to deassert<br>
586 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
587 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
588 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
589 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
590 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
591 Trying to use configured scan chain anyway...<br>
592 Bypassing JTAG setup events due to errors<br>
593 SRST took 2ms to deassert<br>
594 target state: halted<br>
595 target halted in ARM state due to debug-request, current mode: Supervisor<br>
596 cpsr: 0x000000d3 pc: 0x00000000<br>
597 cleared protection for sectors 0 through 7 on flash bank 0<br>
598 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
600 Loading section .text, size 0x1a0 lma 0x0<br>
601 Loading section .rodata, size 0x4 lma 0x1a0<br>
602 Start address 0x0, load size 420<br>
603 Transfer rate: 426 bytes/sec, 210 bytes/write.<br>
604 (gdb) monitor gdb_breakpoint_override hard<br>
605 force hard breakpoints<br>
607 Breakpoint 1 at 0x144: file src/main.c, line 69.<br>
610 Note: automatically using hardware breakpoints for read-only addresses.<br>
612 Breakpoint 1, main () at src/main.c:69<br>
613 warning: Source file is more recent than executable.<br>
615 Current language: auto<br>
616 The current source language is "auto; currently c".<br>
623 <td><a name="DBG006"/>DBG006</td>
626 <td>Hardware breakpoint is set after a reset</td>
627 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
628 <td>In GDB, type <br>
630 (gdb) monitor reset<br>
631 (gdb) monitor reg pc 0x100000<br>
632 pc (/32): 0x00100000<br>
635 where the value inserted in PC is the start address of the application
637 <td>The breakpoint should be reached, typical output:<br>
641 Breakpoint 1, main () at src/main.c:69<br>
647 (gdb) monitor reset init<br>
649 SRST took 2ms to deassert<br>
650 JTAG tap: str912.flash tap/device found: 0x04570041 (mfg: 0x020, part: 0x4570, ver: 0x0)<br>
651 JTAG tap: str912.cpu tap/device found: 0x25966041 (mfg: 0x020, part: 0x5966, ver: 0x2)<br>
652 JTAG tap: str912.bs tap/device found: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
653 JTAG tap: str912.bs UNEXPECTED: 0x2457f041 (mfg: 0x020, part: 0x457f, ver: 0x2)<br>
654 JTAG tap: str912.bs expected 1 of 1: 0x1457f041 (mfg: 0x020, part: 0x457f, ver: 0x1)<br>
655 Trying to use configured scan chain anyway...<br>
656 Bypassing JTAG setup events due to errors<br>
657 SRST took 2ms to deassert<br>
658 target state: halted<br>
659 target halted in ARM state due to debug-request, current mode: Supervisor<br>
660 cpsr: 0x000000d3 pc: 0x00000000<br>
661 cleared protection for sectors 0 through 7 on flash bank 0<br>
662 NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.<br>
666 Breakpoint 1, main () at src/main.c:69<br>
674 <td><a name="DBG007"/>DBG007</td>
677 <td>Single step in ROM</td>
678 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
679 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
681 (gdb) monitor reset<br>
683 Loading section .text, size 0x194 lma 0x100000<br>
684 Start address 0x100040, load size 404<br>
685 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
686 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
687 force hardware breakpoints enabled<br>
689 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
693 Breakpoint 1, main () at src/main.c:69<br>
698 <td>The breakpoint should be reached, typical output:<br>
700 target state: halted<br>
701 target halted in ARM state due to single step, current mode: Supervisor<br>
702 cpsr: 0x60000013 pc: 0x0010013c<br>
710 Breakpoint 2, main () at src/main.c:69<br>
712 Current language: auto<br>
713 The current source language is "auto; currently c".<br>
723 Note: these tests are not designed to test/debug the target, but to test functionalities!
730 <td>Initial state</td>
732 <td>Expected output</td>
733 <td>Actual output</td>
737 <td><a name="RAM001"/>RAM001</td>
740 <td>32 bit Write/read RAM</td>
741 <td>Reset init is working</td>
742 <td>On the telnet interface<br>
743 <code> > mww ram_address 0xdeadbeef 16<br>
747 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
749 > mww 0x0 0xdeadbeef 16<br>
751 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
752 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
753 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
754 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
758 > mww 0x4000000 0xdeadbeef 16<br>
759 > mdw 0x4000000 32 <br>
760 0x04000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
761 0x04000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
762 0x04000040: e580100c e3a01802 e5801010 e3a01018 e5801018 e59f00a8 e59f10a8 e5801000<br>
763 0x04000060: e3a00806 ee2f0f11 e321f0d7 e59fd098 e321f0db e59fd094 e321f0d3 e59fd090<br>
769 <td><a name="RAM002"/>RAM002</td>
772 <td>16 bit Write/read RAM</td>
773 <td>Reset init is working</td>
774 <td>On the telnet interface<br>
775 <code> > mwh ram_address 0xbeef 16<br>
779 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
781 > mwh 0x0 0xbeef 16<br>
783 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
784 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
789 > mwh 0x4000000 0xbeef 16<br>
790 > mdh 0x4000000 32<br>
791 0x04000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
792 0x04000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br>
798 <td><a name="RAM003"/>RAM003</td>
801 <td>8 bit Write/read RAM</td>
802 <td>Reset init is working</td>
803 <td>On the telnet interface<br>
804 <code> > mwb ram_address 0xab 16<br>
808 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
810 > mwb ram_address 0xab 16<br>
811 > mdb ram_address 32<br>
812 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
817 > mwb 0x4000000 0xab 16<br>
818 > mdb 0x4000000 32<br>
819 0x04000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be<br>
828 <H2>Flash access</H2>
835 <td>Initial state</td>
837 <td>Expected output</td>
838 <td>Actual output</td>
842 <td><a name="FLA001"/>FLA001</td>
846 <td>Reset init is working</td>
847 <td>On the telnet interface:<br>
848 <code> > flash probe 0</code>
850 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
851 <code>flash 'ecosflash' found at 0x01000000</code>
856 flash 'str9x' found at 0x00000000<br>
863 <td><a name="FLA002"/>FLA002</td>
867 <td>Reset init is working, flash is probed</td>
868 <td>On the telnet interface<br>
869 <code> > flash fillw 0x1000000 0xdeadbeef 16
872 <td>The commands should execute without error. The output looks like:<br>
874 wrote 64 bytes to 0x01000000 in 11.610000s (0.091516 kb/s)
876 To verify the contents of the flash:<br>
878 > mdw 0x1000000 32<br>
879 0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
880 0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
881 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
882 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
886 > flash fillw 0x0 0xdeadbeef 16 <br>
887 wrote 64 bytes to 0x00000000 in 0.020000s (3.125 kb/s)<br>
889 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
890 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
891 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
892 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
898 <td><a name="FLA003"/>FLA003</td>
902 <td>Reset init is working, flash is probed</td>
903 <td>On the telnet interface<br>
904 <code> > flash erase_address 0x1000000 0x20000
907 <td>The commands should execute without error.<br>
909 erased address 0x01000000 length 131072 in 4.970000s<br>
911 To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
913 > mdw 0x1000000 32<br>
914 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
915 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
916 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
917 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
921 > flash erase_address 0 0x20000<br>
922 erased address 0x00000000 (length 131072) in 1.970000s (64.975 kb/s)<br>
924 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
925 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
926 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
927 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
933 <td><a name="FLA004"/>FLA004</td>
936 <td>Entire flash erase</td>
937 <td>Reset init is working, flash is probed</td>
938 <td>On the telnet interface<br>
939 <code> > flash erase_address 0x0 0x80000
942 <td>The commands should execute without error.<br>
944 erased address 0x01000000 length 8192 in 4.970000s<br>
946 To check that the flash has been erased, read at different addresses. The result should always be 0xff.<br>
948 > mdw 0x1000000 32<br>
949 0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
950 0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
951 0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
952 0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
956 > flash erase_address 0 0x80000<br>
957 erased address 0x00000000 length 524288 in 1.020000s<br>
960 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
961 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
962 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
963 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
968 <td><a name="FLA005"/>FLA005</td>
971 <td>Loading to flash from GDB</td>
972 <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
973 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
975 (gdb) target remote ip:port<br>
976 (gdb) monitor reset<br>
978 Loading section .text, size 0x194 lma 0x100000<br>
979 Start address 0x100040, load size 404<br>
980 Transfer rate: 179 bytes/sec, 404 bytes/write.
981 (gdb) monitor verify_image path_to_elf_file
984 <td>The output should look like:<br>
986 verified 404 bytes in 5.060000s
988 The failure message is something like:<br>
989 <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
994 Loading section .text, size 0x1a0 lma 0x0<br>
995 Loading section .rodata, size 0x4 lma 0x1a0<br>
996 Start address 0x0, load size 420<br>
997 Transfer rate: 425 bytes/sec, 210 bytes/write.<br>
998 (gdb) moni verify_image /tftp/10.0.0.194/test_rom.elf<br>
999 verified 420 bytes in 0.350000s (1.172 kb/s)<br>