3 <title>Test results for revision 1.62</title>
17 <td>Initial state</td>
19 <td>Expected output</td>
20 <td>Actual output</td>
24 <td><a name="CON001"/>CON001</td>
27 <td>Telnet connection</td>
28 <td>Power on, jtag target attached</td>
29 <td>On console, type<br><code>telnet ip port</code></td>
30 <td><code>Open On-Chip Debugger<br>></code></td>
31 <td><code>Open On-Chip Debugger<br>></code></td>
35 <td><a name="CON002"/>CON002</td>
38 <td>GDB server connection</td>
39 <td>Power on, jtag target attached</td>
40 <td>On GDB console, type<br><code>target remote ip:port</code></td>
41 <td><code>Remote debugging using 10.0.0.73:3333</code></td>
43 (gdb) tar remo 10.0.0.73:3333<br>
44 Remote debugging using 10.0.0.73:3333<br>
45 0x00100174 in ?? ()<br>
58 <td>Initial state</td>
60 <td>Expected output</td>
61 <td>Actual output</td>
65 <td><a name="RES001"/>RES001</td>
68 <td>Reset halt on a blank target</td>
69 <td>Erase all the content of the flash</td>
70 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
71 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
75 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
76 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
77 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
78 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
80 SRST took 2ms to deassert<br>
81 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
82 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
83 target state: halted<br>
84 target halted in ARM state due to debug request, current mode: Supervisor<br>
85 cpsr: 0x600000d3 pc: 0x000003c4<br>
92 <td><a name="RES002"/>RES002</td>
95 <td>Reset init on a blank target</td>
96 <td>Erase all the content of the flash</td>
97 <td>Connect via the telnet interface and type <br><code>reset init</code></td>
98 <td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
102 SRST took 2ms to deassert<br>
103 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
104 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
105 target state: halted<br>
106 target halted in ARM state due to debug request, current mode: Supervisor<br>
107 cpsr: 0x600000d3 pc: 0x000003c0<br>
112 NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>
115 <td><a name="RES003"/>RES003</td>
118 <td>Reset after a power cycle of the target</td>
119 <td>Reset the target then power cycle the target</td>
120 <td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
121 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
124 Sensed nSRST asserted<br>
125 Sensed power dropout.<br>
126 target state: halted<br>
127 target halted in ARM state due to debug request, current mode: Supervisor<br>
128 cpsr: 0xf00000d3 pc: 0xd5dff7e6<br>
129 Sensed power restore.<br>
130 Sensed nSRST deasserted<br>
132 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
133 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
134 target state: halted<br>
135 target halted in ARM state due to debug request, current mode: Supervisor<br>
136 cpsr: 0xf00000d3 pc: 0x0000072c<br>
143 <td><a name="RES004"/>RES004</td>
146 <td>Reset halt on a blank target where reset halt is supported</td>
147 <td>Erase all the content of the flash</td>
148 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
149 <td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
153 SRST took 2ms to deassert<br>
154 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
155 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
156 target state: halted<br>
157 target halted in ARM state due to debug request, current mode: Supervisor<br>
158 cpsr: 0x300000d3 pc: 0x000003c0
164 <td><a name="RES005"/>RES005</td>
167 <td>Reset halt on a blank target using return clock</td>
168 <td>Erase all the content of the flash, set the configuration script to use RCLK</td>
169 <td>Connect via the telnet interface and type <br><code>reset halt</code></td>
170 <td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
176 SRST took 2ms to deassert<br>
177 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
178 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
179 target state: halted<br>
180 target halted in ARM state due to debug request, current mode: Supervisor<br>
181 cpsr: 0x300000d3 pc: 0x000003c0<br>
182 executing event/sam7s256_reset.script<br>
197 <td>Initial state</td>
199 <td>Expected output</td>
200 <td>Actual output</td>
204 <td><a name="SPD001"/>SPD001</td>
207 <td>16MHz on normal operation</td>
208 <td>Reset init the target according to RES002 </td>
209 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
210 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
214 jtag_speed 4 => JTAG clk=16.000000<br>
217 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
218 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
219 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
220 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
227 <td><a name="SPD002"/>SPD002</td>
230 <td>8MHz on normal operation</td>
231 <td>Reset init the target according to RES002 </td>
232 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
233 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
237 jtag_speed 8 => JTAG clk=8.000000<br>
240 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
241 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
242 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
243 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
249 <td><a name="SPD003"/>SPD003</td>
252 <td>4MHz on normal operation</td>
253 <td>Reset init the target according to RES002 </td>
254 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
255 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
259 jtag_speed 16 => JTAG clk=4.000000<br>
262 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
263 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
264 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
265 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
272 <td><a name="SPD004"/>SPD004</td>
275 <td>2MHz on normal operation</td>
276 <td>Reset init the target according to RES002 </td>
277 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
278 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
282 jtag_speed 32 => JTAG clk=2.000000<br>
285 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
286 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
287 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
288 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
295 <td><a name="SPD005"/>SPD005</td>
298 <td>RCLK on normal operation</td>
299 <td>Reset init the target according to RES002 </td>
300 <td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
301 <td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
307 0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
308 0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
309 0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
310 0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
325 <td>Initial state</td>
327 <td>Expected output</td>
328 <td>Actual output</td>
332 <td><a name="DBG001"/>DBG001</td>
335 <td>Load is working</td>
336 <td>Reset init is working, RAM is accesible, GDB server is started</td>
337 <td>On the console of the OS: <br>
338 <code>arm-elf-gdb test_ram.elf</code><br>
339 <code>(gdb) target remote ip:port</code><br>
340 <code>(gdb) load</load>
342 <td>Load should return without error, typical output looks like:<br>
344 Loading section .text, size 0x14c lma 0x0<br>
345 Start address 0x40, load size 332<br>
346 Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
351 Loading section .text, size 0x194 lma 0x200000<br>
352 Start address 0x200040, load size 404<br>
353 Transfer rate: 443 bytes/sec, 404 bytes/write.<br>
360 <td><a name="DBG002"/>DBG002</td>
363 <td>Software breakpoint</td>
364 <td>Load the test_ram.elf application, use instructions from GDB001</td>
365 <td>In the GDB console:<br>
367 (gdb) monitor arm7_9 dbgrq enable<br>
368 software breakpoints enabled<br>
370 Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
375 <td>The software breakpoint should be reached, a typical output looks like:<br>
377 Breakpoint 1, main () at src/main.c:69<br>
383 (gdb) monitor arm7_9 dbgrq enable<br>
384 use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled<br>
386 Breakpoint 1 at 0x200134: file src/main.c, line 69.<br>
390 Breakpoint 1, main () at src/main.c:69<br>
392 Current language: auto<br>
393 The current source language is "auto; currently c".<br>
400 <td><a name="DBG003"/>DBG003</td>
403 <td>Single step in a RAM application</td>
404 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
405 <td>In GDB, type <br><code>(gdb) step</code></td>
406 <td>The next instruction should be reached, typical output:<br>
423 <td><a name="DBG004"/>DBG004</td>
426 <td>Software break points are working after a reset</td>
427 <td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
428 <td>In GDB, type <br><code>
429 (gdb) monitor reset init<br>
433 <td>The breakpoint should be reached, typical output:<br>
435 Breakpoint 1, main () at src/main.c:69<br>
440 (gdb) monitor reset init<br>
441 JTAG tap: sam7x256.cpu tap/device found: 0x3f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x3)<br>
442 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
443 target state: halted<br>
444 target halted in ARM state due to debug-request, current mode: Supervisor<br>
445 cpsr: 0x600000d3 pc: 0x0000031c<br>
447 Loading section .text, size 0x194 lma 0x200000<br>
448 Start address 0x200040, load size 404<br>
449 Transfer rate: 26 KB/sec, 404 bytes/write.<br>
453 Breakpoint 1, main () at src/main.c:69<br>
460 <td><a name="DBG005"/>DBG005</td>
463 <td>Hardware breakpoint</td>
464 <td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
465 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
467 (gdb) monitor reset init<br>
469 Loading section .text, size 0x194 lma 0x100000<br>
470 Start address 0x100040, load size 404<br>
471 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
472 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
473 force hardware breakpoints enabled<br>
475 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
479 <td>The breakpoint should be reached, typical output:<br>
483 Breakpoint 1, main () at src/main.c:69<br>
489 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
490 force hardware breakpoints enabled<br>
492 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
495 Note: automatically using hardware breakpoints for read-only addresses.<br>
496 target state: halted<br>
497 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
498 cpsr: 0x60000013 pc: 0x00100134<br>
500 Breakpoint 1, main () at src/main.c:69<br>
508 <td><a name="DBG006"/>DBG006</td>
511 <td>Hardware breakpoint is set after a reset</td>
512 <td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
513 <td>In GDB, type <br>
515 (gdb) monitor reset<br>
516 (gdb) monitor reg pc 0x100000<br>
517 pc (/32): 0x00100000<br>
520 where the value inserted in PC is the start address of the application
522 <td>The breakpoint should be reached, typical output:<br>
526 Breakpoint 1, main () at src/main.c:69<br>
532 (gdb) monitor reset init<br>
533 SRST took 3ms to deassert<br>
534 JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
535 srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
536 target state: halted<br>
537 target halted in ARM state due to debug request, current mode: Supervisor<br>
538 cpsr: 0x60000013 pc: 0x00100168<br>
539 executing event/sam7s256_reset.script<br>
540 (gdb) monitor reg pc 0x100000<br>
541 pc (/32): 0x00100000<br>
544 target state: halted<br>
545 target halted in ARM state due to single step, current mode: Supervisor<br>
546 cpsr: 0x60000013 pc: 0x00100040<br>
547 target state: halted<br>
548 target halted in ARM state due to breakpoint, current mode: Supervisor<br>
549 cpsr: 0x60000013 pc: 0x00100134<br>
551 Breakpoint 1, main () at src/main.c:69<br>
559 <td><a name="DBG007"/>DBG007</td>
562 <td>Single step in ROM</td>
563 <td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
564 <td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
566 (gdb) monitor reset<br>
568 Loading section .text, size 0x194 lma 0x100000<br>
569 Start address 0x100040, load size 404<br>
570 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
571 (gdb) monitor arm7_9 force_hw_bkpts enable<br>
572 force hardware breakpoints enabled<br>
574 Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
578 Breakpoint 1, main () at src/main.c:69<br>
583 <td>The breakpoint should be reached, typical output:<br>
585 target state: halted<br>
586 target halted in ARM state due to single step, current mode: Supervisor<br>
587 cpsr: 0x60000013 pc: 0x0010013c<br>
592 Breakpoint 1, main () at src/main.c:69<br>
595 target state: halted<br>
596 target halted in ARM state due to single step, current mode: Supervisor<br>
597 cpsr: 0x60000013 pc: 0x00100138<br>
598 target state: halted<br>
599 target halted in ARM state due to single step, current mode: Supervisor<br>
600 cpsr: 0x60000013 pc: 0x0010013c<br>
609 Note: these tests are not designed to test/debug the target, but to test functionalities!
616 <td>Initial state</td>
618 <td>Expected output</td>
619 <td>Actual output</td>
623 <td><a name="RAM001"/>RAM001</td>
626 <td>32 bit Write/read RAM</td>
627 <td>Reset init is working</td>
628 <td>On the telnet interface<br>
629 <code> > mww ram_address 0xdeadbeef 16<br>
633 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
635 > mww 0x0 0xdeadbeef 16<br>
637 0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
638 0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
639 0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
640 0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
644 > mww 0x00200000 0xdeadbeef 16<br>
645 > mdw 0x00200000 32<br>
646 0x00200000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
647 0x00200020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
648 0x00200040: e59f10b4 e3a00902 e5810004 e59f00ac e59f10ac e5810000 e3e010ff e59f00a4<br>
649 0x00200060: e5810060 e59f10a0 e3e00000 e5810130 e5810124 e321f0db e59fd090 e321f0d7
654 <td><a name="RAM002"/>RAM002</td>
657 <td>16 bit Write/read RAM</td>
658 <td>Reset init is working</td>
659 <td>On the telnet interface<br>
660 <code> > mwh ram_address 0xbeef 16<br>
664 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
666 > mwh 0x0 0xbeef 16<br>
668 0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
669 0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
674 > mwh 0x00200000 0xbeef 16<br>
675 > mdh 0x00200000 32<br>
676 0x00200000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
677 0x00200020: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
682 <td><a name="RAM003"/>RAM003</td>
685 <td>8 bit Write/read RAM</td>
686 <td>Reset init is working</td>
687 <td>On the telnet interface<br>
688 <code> > mwb ram_address 0xab 16<br>
692 <td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
694 > mwb ram_address 0xab 16<br>
695 > mdb ram_address 32<br>
696 0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
701 > mwb 0x00200000 0xab 16<br>
702 > mdb 0x00200000 32<br>
703 0x00200000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
711 <H2>Flash access</H2>
718 <td>Initial state</td>
720 <td>Expected output</td>
721 <td>Actual output</td>
725 <td><a name="FLA001"/>FLA001</td>
729 <td>Reset init is working</td>
730 <td>On the telnet interface:<br>
731 <code> > flash probe 0</code>
733 <td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
734 <code>flash 'ecosflash' found at 0x01000000</code>
739 flash 'at91sam7' found at 0x00100000
745 <td><a name="FLA002"/>FLA002</td>
749 <td>Reset init is working, flash is probed</td>
750 <td>On the telnet interface<br>
751 <code> > flash fillw 0x100000 0xdeadbeef 16
754 <td>The commands should execute without error. The output looks like:<br>
756 wrote 64 bytes to 0x0100000 in 11.610000s (0.091516 kb/s)
758 To verify the contents of the flash:<br>
760 > mdw 0x100000 32<br>
761 0x0100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
762 0x0100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
763 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
764 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
768 > flash fillw 0x100000 0xdeadbeef 16<br>
769 wrote 64 bytes to 0x00100000 in 0.040000s (26.562500 kb/s)<br>
770 > mdw 0x100000 32<br>
771 0x00100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
772 0x00100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
773 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
774 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
780 <td><a name="FLA003"/>FLA003</td>
784 <td>Reset init is working, flash is probed</td>
785 <td>On the telnet interface<br>
786 <code> > flash erase_address 0x100000 0x2000
789 <td>The commands should execute without error.<br>
791 erased address 0x0100000 length 8192 in 4.970000s
793 To check that the flash has been erased, read at different addresses. The result should always be 0xff.
795 > mdw 0x100000 32<br>
796 0x0100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
797 0x0100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
798 0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
799 0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
803 > flash erase_address 0x100000 0x2000<br>
804 erased address 0x00100000 length 8192 in 0.020000s<br>
805 > mdw 0x100000 32<br>
806 0x00100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
807 0x00100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
808 0x00100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
809 0x00100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
815 <td><a name="FLA004"/>FLA004</td>
818 <td>Loading to flash from GDB</td>
819 <td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
820 <td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
822 (gdb) target remote ip:port<br>
823 (gdb) monitor reset halt<br>
825 Loading section .text, size 0x194 lma 0x100000<br>
826 Start address 0x100040, load size 404<br>
827 Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
828 (gdb) monitor verify_image path_to_elf_file
831 <td>The output should look like:<br>
833 verified 404 bytes in 5.060000s
835 The failure message is something like:<br>
836 <code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
841 Loading section .text, size 0x194 lma 0x100000<br>
842 Start address 0x100040, load size 404<br>
843 Transfer rate: 4 KB/sec, 404 bytes/write.<br>
844 (gdb) moni verify_image /tftp/10.0.0.9/c:/temp/testing/examples/SAM7S256Test/test_rom.elf<br>
845 verified 404 bytes in 0.570000s