1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Cadence virtual debug interface
5 if {![info exists _CORES]} {
8 if {![info exists _CHIPNAME]} {
11 set _TARGETNAME $_CHIPNAME.cpu
12 set _CTINAME $_CHIPNAME.cti
14 set DBGBASE {0x80810000 0x80910000}
15 set CTIBASE {0x80820000 0x80920000}
17 dap create $_CHIPNAME.dap -chain-position $_TARGETNAME
18 $_CHIPNAME.dap apsel 1
20 for { set _core 0 } { $_core < $_CORES } { incr _core } \
22 cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 -baseaddr [lindex $CTIBASE $_core]
23 set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
24 -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core -coreid $_core"
26 # non-boot core examination may fail
27 set _command "$_command -defer-examine"
28 set _smp_command "$_smp_command $_TARGETNAME.$_core"
30 set _smp_command "target smp $_TARGETNAME.$_core"
36 # default target is core 0
37 targets $_TARGETNAME.0