1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * AM642: https://www.ti.com/lit/pdf/spruim2
12 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
15 if { [info exists SOC] } {
21 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
22 if { [info exists V8_SMP_DEBUG] } {
23 set _v8_smp_debug $V8_SMP_DEBUG
30 # CM3 the very first processor - all current SoCs have it.
31 set CM3_CTIBASE {0x3C016000}
33 # M3 power-ap unlock offsets
34 set _m3_ap_unlock_offsets {0xf0 0x44}
36 # All the ARMV8s are the next processors.
37 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
38 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
39 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
41 # And we add up the R5s
42 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
43 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
44 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
47 set CM4_CTIBASE {0x20001000}
49 # M4 may be present on some very few SoCs
51 # M4 power-ap unlock offsets
52 set _m4_ap_unlock_offsets {0xf0 0x60}
54 # Set configuration overrides for each SOC
58 set _K3_DAP_TAPID 0x0bb5a02f
60 # AM654 has 2 clusters of 2 A53 cores each.
61 set _armv8_cpu_name a53
64 # AM654 has 1 cluster of 2 R5s cores.
67 set _mcu_base_core_id 0
69 set _main0_base_core_id 0
71 set _main1_base_core_id 0
73 # M3 power-ap unlock offsets
74 set _m3_ap_unlock_offsets {0xf0 0x50}
78 set _K3_DAP_TAPID 0x0bb3802f
80 # AM642 has 1 clusters of 2 A53 cores each.
81 set _armv8_cpu_name a53
83 set ARMV8_DBGBASE {0x90010000 0x90110000}
84 set ARMV8_CTIBASE {0x90020000 0x90120000}
86 # AM642 has 2 cluster of 2 R5s cores.
89 set _mcu_base_core_id 0
91 set _main0_base_core_id 0
93 set _main1_base_core_id 2
94 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
95 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
102 set _K3_DAP_TAPID 0x0bb6402f
103 # J721E has 1 cluster of 2 A72 cores.
104 set _armv8_cpu_name a72
107 # J721E has 3 clusters of 2 R5 cores each.
110 set _mcu_base_core_id 0
111 set _main0_r5_cores 2
112 set _main0_base_core_id 2
113 set _main1_r5_cores 2
114 set _main1_base_core_id 4
118 set _K3_DAP_TAPID 0x0bb6d02f
120 # J7200 has 1 cluster of 2 A72 cores.
121 set _armv8_cpu_name a72
124 # J7200 has 2 clusters of 2 R5 cores each.
127 set _mcu_base_core_id 0
128 set _main0_r5_cores 2
129 set _main0_base_core_id 2
130 set _main1_r5_cores 0
131 set _main1_base_core_id 0
132 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
133 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
136 set CM3_CTIBASE {0x20001000}
139 echo "'$_soc' is invalid!"
143 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
144 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
146 set _TARGETNAME $_CHIPNAME.cpu
148 set _CTINAME $_CHIPNAME.cti
150 # M3 is always present
151 cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
152 target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
153 $_TARGETNAME.m3 configure -event reset-assert { }
155 proc m3_up { args } {
156 # To access M3, we need to enable the JTAG access for the same.
157 # Ensure Power-AP unlocked
158 $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
159 $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 1] 0x00102098
161 $::_TARGETNAME.m3 arp_examine
164 set _v8_smp_targets ""
166 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
168 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
169 -baseaddr [lindex $ARMV8_CTIBASE $_core]
171 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
172 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
174 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
177 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
178 set _armv8_up_cmd "$_armv8_cpu_name"_up
179 # Available if V8_SMP_DEBUG is set to non-zero value
180 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
182 if { $_v8_smp_debug == 0 } {
183 proc $_armv8_up_cmd { args } {
184 foreach { _core } [set args] {
185 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
186 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
190 proc $_armv8_smp_cmd { args } {
191 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
192 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
193 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
194 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
196 # Set Default target are core 0
197 targets $::_TARGETNAME.$::_armv8_cpu_name.0
201 target smp $:::_v8_smp_targets
204 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
205 cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
206 -baseaddr [lindex $R5_CTIBASE $_core]
208 # inactive core examination will fail - wait till startup of additional core
209 target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
210 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
213 if { $_mcu_r5_cores != 0 } {
214 proc mcu_r5_up { args } {
215 foreach { _core } [set args] {
216 set _core [expr {$_core + $::_mcu_base_core_id}]
217 $::_TARGETNAME.r5.$_core arp_examine
218 $::_TARGETNAME.r5.$_core cortex_r4 dbginit
223 if { $_main0_r5_cores != 0 } {
224 proc main0_r5_up { args } {
225 foreach { _core } [set args] {
226 set _core [expr {$_core + $::_main0_base_core_id}]
227 $::_TARGETNAME.r5.$_core arp_examine
228 $::_TARGETNAME.r5.$_core cortex_r4 dbginit
233 if { $_main1_r5_cores != 0 } {
234 proc main1_r5_up { args } {
235 foreach { _core } [set args] {
236 set _core [expr {$_core + $::_main1_base_core_id}]
237 $::_TARGETNAME.r5.$_core arp_examine
238 $::_TARGETNAME.r5.$_core cortex_r4 dbginit
243 if { $_mcu_m4_cores != 0 } {
244 cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
245 target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
246 $_TARGETNAME.m4 configure -event reset-assert { }
248 proc m4_up { args } {
249 # To access M4, we need to enable the JTAG access for the same.
250 # Ensure Power-AP unlocked
251 $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
252 $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
254 $::_TARGETNAME.m4 arp_examine