2 # Texas Instruments DaVinci family: TMS320DM365
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
11 # For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
12 # are enabled without making ICEpick route ARM and ETB into the JTAG chain.
14 # Also note: when running without RTCK before the PLLs are set up, you
15 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
17 source [find target/icepick.cfg]
21 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
22 if { [info exists ETB_TAPID ] } {
23 set _ETB_TAPID $ETB_TAPID
25 set _ETB_TAPID 0x2b900f0f
27 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
28 -expected-id $_ETB_TAPID $EMU01
29 jtag configure $_CHIPNAME.etb -event tap-enable \
30 "icepick_c_tapenable $_CHIPNAME.jrc 1"
32 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
33 if { [info exists CPU_TAPID ] } {
34 set _CPU_TAPID $CPU_TAPID
36 set _CPU_TAPID 0x0792602f
38 jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
39 -expected-id $_CPU_TAPID $EMU01
40 jtag configure $_CHIPNAME.arm -event tap-enable \
41 "icepick_c_tapenable $_CHIPNAME.jrc 0"
43 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
44 if { [info exists JRC_TAPID ] } {
45 set _JRC_TAPID $JRC_TAPID
47 set _JRC_TAPID 0x0b83e02f
49 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
50 -expected-id $_JRC_TAPID
54 # various symbol definitions, to avoid hard-wiring addresses
55 # and enable some sharing of DaVinci-family utility code
57 set dm365 [ dict create ]
59 # Physical addresses for controllers and memory
60 # (Some of these are valid for many DaVinci family chips)
61 dict set dm365 sram0 0x00010000
62 dict set dm365 sram1 0x00014000
63 dict set dm365 sysbase 0x01c40000
64 dict set dm365 pllc1 0x01c40800
65 dict set dm365 pllc2 0x01c40c00
66 dict set dm365 psc 0x01c41000
67 dict set dm365 gpio 0x01c67000
68 dict set dm365 a_emif 0x01d10000
69 dict set dm365 a_emif_cs0 0x02000000
70 dict set dm365 a_emif_cs1 0x04000000
71 dict set dm365 ddr_emif 0x20000000
72 dict set dm365 ddr 0x80000000
74 source [find target/davinci.cfg]
77 # GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
78 # and the ETB memory (4K) are other options, while trace is unused.
79 set _TARGETNAME $_CHIPNAME.arm
81 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
83 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
84 # and that the work area is used only with a kernel mmu context ...
85 $_TARGETNAME configure \
86 -work-area-virt [expr 0xfffe0000 + 0x4000] \
87 -work-area-phys [dict get $dm365 sram1] \
88 -work-area-size 0x4000 \
92 arm7_9 fast_memory_access enable
93 arm7_9 dcc_downloads enable
96 etm config $_TARGETNAME 16 normal full etb
97 etb config $_TARGETNAME $_CHIPNAME.etb