2 # For more information about the configuration files, take a look at:
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 if { [info exists ENDIAN] } {
17 # jtag speed. We need to stick to 16kHz until we've finished reset.
23 #use combined on interfaces or targets that can't set TRST/SRST separately
24 #reset_config trst_and_srst
26 if { [info exists FLASHTAPID ] } {
27 set _FLASHTAPID $FLASHTAPID
29 set _FLASHTAPID 0x04570041
31 jtag newtap $_CHIPNAME flash \
32 -irlen 8 -ircapture 0x1 -irmask 0x1 \
33 -expected-id $_FLASHTAPID
35 if { [info exists CPUTAPID ] } {
36 set _CPUTAPID $CPUTAPID
38 set _CPUTAPID 0x25966041
40 jtag newtap $_CHIPNAME cpu \
41 -irlen 4 -ircapture 0x1 -irmask 0xf \
42 -expected-id $_CPUTAPID
45 if { [info exists BSTAPID ] } {
46 set _BSTAPID1 $BSTAPID
47 set _BSTAPID2 $BSTAPID
49 set _BSTAPID1 0x1457f041
50 set _BSTAPID2 0x2457f041
52 jtag newtap $_CHIPNAME bs \
53 -irlen 5 -ircapture 0x1 -irmask 0x1 \
54 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
56 set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
57 target create $_TARGETNAME arm966e \
59 -chain-position $_TARGETNAME \
62 $_TARGETNAME configure -event reset-start { jtag_rclk 16 }
64 proc str9x_config { } {
65 # -- Enable 96K RAM w/:
66 # PFQBC enabled / DTCM & AHB wait-states disabled
68 # PFQBC disabled / DTCM & AHB wait-states enabled
69 #mww 0x5C002034 0x0196
72 str9x flash_config 0 3 2 0 0x40000
74 #str9x flash_config 0 4 2 0 0x80000
83 $_TARGETNAME configure -event reset-init str9x_init
85 $_TARGETNAME configure \
87 -work-area-phys 0x50000000 \
88 -work-area-size 16384 \
91 #flash bank str9x <base> <size> 0 0 <target#> <variant>
92 flash bank str9x 0x00000000 0x00040000 0 0 0
93 flash bank str9x 0x00040000 0x00008000 0 0 0