1 # SPDX-License-Identifier: GPL-2.0-or-later
5 if { [info exists CHIPNAME] } {
6 set _CHIPNAME $CHIPNAME
11 if { [info exists ENDIAN] } {
17 if { [info exists CPUTAPID] } {
18 set _CPUTAPID $CPUTAPID
20 set _CPUTAPID 0x4f1f0041
26 #use combined on interfaces or targets that can't set TRST/SRST separately
27 reset_config trst_and_srst srst_pulls_trst
31 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
33 #jtag nTRST and nSRST delay
34 adapter srst delay 500
37 set _TARGETNAME $_CHIPNAME.cpu
38 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0
40 $_TARGETNAME configure -event reset-start { adapter speed 10 }
41 $_TARGETNAME configure -event reset-init {
45 # Because the hardware cannot be interrogated for the protection state
46 # of sectors, initialize all the sectors to be unprotected. The initial
47 # state is reflected by the driver, too.
48 flash protect 0 0 last off
49 flash protect 1 0 last off
51 $_TARGETNAME configure -event gdb-flash-erase-start {
52 flash protect 0 0 7 off
53 flash protect 1 0 1 off
56 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
58 #flash bank <driver> <base> <size> <chip_width> <bus_width>
59 set _FLASHNAME $_CHIPNAME.flash0
60 flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
61 set _FLASHNAME $_CHIPNAME.flash1
62 flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
64 # Serial NOR on SMI CS0.
65 set _FLASHNAME $_CHIPNAME.snor
66 flash bank $_FLASHNAME stmsmi 0x80000000 0 0 0 $_TARGETNAME
68 source [find mem_helper.tcl]
71 mmw 0x60000030 0x01000000 0x00000000; # enable clock for GPIO regs
72 mmw 0xffffe420 0x00000001 0x00000000; # set SMI_EN bit
73 mmw 0x90000000 0x00000001 0x00000000; # set BLOCK_EN_1