1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32wlx family
6 # stm32wl devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32wlx
17 if { [info exists DUAL_CORE] } {
18 set $_CHIPNAME.DUAL_CORE $DUAL_CORE
21 set $_CHIPNAME.DUAL_CORE 0
24 if { [info exists WKUP_CM0P] } {
25 set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
28 set $_CHIPNAME.WKUP_CM0P 0
31 # Issue a warning when hla is used, and fallback to single core configuration
32 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
33 echo "Warning : hla does not support multicore debugging"
34 set $_CHIPNAME.DUAL_CORE 0
35 set $_CHIPNAME.WKUP_CM0P 0
38 # setup the Work-area start address and size
39 # Work-area is a space in RAM used for flash programming
41 # Memory map for known devices:
42 # STM32WL x5JC x5JB x5J8
48 if { [info exists WORKAREASIZE] } {
49 set _WORKAREASIZE $WORKAREASIZE
51 set _WORKAREASIZE 0x2000
54 # Use SRAM2 as work area (some devices do not have SRAM1):
55 set WORKAREASTART_CM4 0x20008000
56 set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
59 if { [info exists CPUTAPID] } {
60 set _CPUTAPID $CPUTAPID
63 set _CPUTAPID 0x6ba00477
65 # SWD IDCODE (single drop, arm)
66 set _CPUTAPID 0x6ba02477
70 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
71 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
74 jtag newtap $_CHIPNAME bs -irlen 5
77 target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
79 $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
81 flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
82 flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
85 # if srst is not fitted use SYSRESETREQ to
86 # perform a soft reset
87 $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
90 $_CHIPNAME.cpu0 configure -event reset-init {
91 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
92 # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
93 # 2 WS compliant with VOS=Range1 and 24 MHz.
94 mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
95 mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
96 # Boost JTAG frequency
100 $_CHIPNAME.cpu0 configure -event reset-start {
101 # Reset clock is MSI (4 MHz)
105 $_CHIPNAME.cpu0 configure -event examine-end {
106 # Enable debug during low power modes (uses more power)
107 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
108 mmw 0xE0042004 0x00000007 0
110 # Stop watchdog counters during halt
111 # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
112 mmw 0xE004203C 0x00001800 0
114 set _CHIPNAME [stm32wlx_get_chipname]
115 global $_CHIPNAME.WKUP_CM0P
117 if {[set $_CHIPNAME.WKUP_CM0P]} {
122 $_CHIPNAME.cpu0 configure -event trace-config {
126 if {[set $_CHIPNAME.DUAL_CORE]} {
127 target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
129 $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
131 flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
132 flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
135 # if srst is not fitted use SYSRESETREQ to
136 # perform a soft reset
137 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
140 proc stm32wlx_wkup_cm0p {} {
141 set _CHIPNAME [stm32wlx_get_chipname]
143 # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
145 stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
149 # get _CHIPNAME from current target
150 proc stm32wlx_get_chipname {} {
151 set t [target current]
152 set sep [string last "." $t]
156 return [string range $t 0 [expr {$sep - 1}]]
159 # like mrw, but with target selection
160 proc stm32wlx_mrw {used_target reg} {
161 return [$used_target read_memory $reg 32 1]
164 # like mmw, but with target selection
165 proc stm32wlx_mmw {used_target reg setbits clearbits} {
166 set old [stm32wlx_mrw $used_target $reg]
167 set new [expr {($old & ~$clearbits) | $setbits}]
168 $used_target mww $reg $new
171 # Make sure that cpu0 is selected
172 targets $_CHIPNAME.cpu0
174 # Common knowledges tells JTAG speed should be <= F_CPU/6.
175 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
178 # Note that there is a pretty wide band where things are
179 # more or less stable, see http://openocd.zylin.com/#/c/3366/
182 adapter srst delay 100
187 reset_config srst_nogate