1 # script for stm32wlx family
4 # stm32wl devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32wlx
15 if { [info exists DUAL_CORE] } {
16 set $_CHIPNAME.DUAL_CORE $DUAL_CORE
19 set $_CHIPNAME.DUAL_CORE 0
22 if { [info exists WKUP_CM0P] } {
23 set $_CHIPNAME.WKUP_CM0P $WKUP_CM0P
26 set $_CHIPNAME.WKUP_CM0P 0
29 # Issue a warning when hla is used, and fallback to single core configuration
30 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
31 echo "Warning : hla does not support multicore debugging"
32 set $_CHIPNAME.DUAL_CORE 0
33 set $_CHIPNAME.WKUP_CM0P 0
36 # setup the Work-area start address and size
37 # Work-area is a space in RAM used for flash programming
39 # Memory map for known devices:
40 # STM32WL x5JC x5JB x5J8
46 if { [info exists WORKAREASIZE] } {
47 set _WORKAREASIZE $WORKAREASIZE
49 set _WORKAREASIZE 0x2000
52 # Use SRAM2 as work area (some devices do not have SRAM1):
53 set WORKAREASTART_CM4 0x20008000
54 set WORKAREASTART_CM0P [expr {$WORKAREASTART_CM4 + $_WORKAREASIZE}]
57 if { [info exists CPUTAPID] } {
58 set _CPUTAPID $CPUTAPID
61 set _CPUTAPID 0x6ba00477
63 # SWD IDCODE (single drop, arm)
64 set _CPUTAPID 0x6ba02477
68 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
69 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
72 jtag newtap $_CHIPNAME bs -irlen 5
75 target create $_CHIPNAME.cpu0 cortex_m -endian little -dap $_CHIPNAME.dap
77 $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM4 -work-area-size $_WORKAREASIZE -work-area-backup 0
79 flash bank $_CHIPNAME.flash.cpu0 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu0
80 flash bank $_CHIPNAME.otp.cpu0 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu0
83 # if srst is not fitted use SYSRESETREQ to
84 # perform a soft reset
85 $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
88 $_CHIPNAME.cpu0 configure -event reset-init {
89 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
90 # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
91 # 2 WS compliant with VOS=Range1 and 24 MHz.
92 mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
93 mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
94 # Boost JTAG frequency
98 $_CHIPNAME.cpu0 configure -event reset-start {
99 # Reset clock is MSI (4 MHz)
103 $_CHIPNAME.cpu0 configure -event examine-end {
104 # Enable debug during low power modes (uses more power)
105 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
106 mmw 0xE0042004 0x00000007 0
108 # Stop watchdog counters during halt
109 # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
110 mmw 0xE004203C 0x00001800 0
112 set _CHIPNAME [stm32wlx_get_chipname]
113 global $_CHIPNAME.WKUP_CM0P
115 if {[set $_CHIPNAME.WKUP_CM0P]} {
120 $_CHIPNAME.cpu0 configure -event trace-config {
124 if {[set $_CHIPNAME.DUAL_CORE]} {
125 target create $_CHIPNAME.cpu1 cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
127 $_CHIPNAME.cpu0 configure -work-area-phys $WORKAREASTART_CM0P -work-area-size $_WORKAREASIZE -work-area-backup 0
129 flash bank $_CHIPNAME.flash.cpu1 stm32l4x 0x08000000 0 0 0 $_CHIPNAME.cpu1
130 flash bank $_CHIPNAME.otp.cpu1 stm32l4x 0x1fff7000 0 0 0 $_CHIPNAME.cpu1
133 # if srst is not fitted use SYSRESETREQ to
134 # perform a soft reset
135 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
138 proc stm32wlx_wkup_cm0p {} {
139 set _CHIPNAME [stm32wlx_get_chipname]
141 # enable CPU2 boot after reset and after wakeup from Stop or Standby mode
143 stm32wlx_mmw $_CHIPNAME.cpu0 0x5800040C 0x00008000 0
147 # get _CHIPNAME from current target
148 proc stm32wlx_get_chipname {} {
149 set t [target current]
150 set sep [string last "." $t]
154 return [string range $t 0 [expr {$sep - 1}]]
157 # like mrw, but with target selection
158 proc stm32wlx_mrw {used_target reg} {
159 return [$used_target read_memory $reg 32 1]
162 # like mmw, but with target selection
163 proc stm32wlx_mmw {used_target reg setbits clearbits} {
164 set old [stm32wlx_mrw $used_target $reg]
165 set new [expr {($old & ~$clearbits) | $setbits}]
166 $used_target mww $reg $new
169 # Make sure that cpu0 is selected
170 targets $_CHIPNAME.cpu0
172 # Common knowledges tells JTAG speed should be <= F_CPU/6.
173 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
176 # Note that there is a pretty wide band where things are
177 # more or less stable, see http://openocd.zylin.com/#/c/3366/
180 adapter srst delay 100
185 reset_config srst_nogate