1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32wbx family
6 # stm32wb devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32wbx
19 # Work-area is a space in RAM used for flash programming
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x10000
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
32 set _CPUTAPID 0x6ba00477
34 # SWD IDCODE (single drop, arm)
35 set _CPUTAPID 0x6ba02477
39 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
40 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
43 jtag newtap $_CHIPNAME bs -irlen 5
46 set _TARGETNAME $_CHIPNAME.cpu
47 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
49 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
51 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
52 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
54 # Common knowledges tells JTAG speed should be <= F_CPU/6.
55 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
58 # Note that there is a pretty wide band where things are
59 # more or less stable, see http://openocd.zylin.com/#/c/3366/
62 adapter srst delay 100
67 reset_config srst_nogate
70 # if srst is not fitted use SYSRESETREQ to
71 # perform a soft reset
72 cortex_m reset_config sysresetreq
75 $_TARGETNAME configure -event reset-init {
76 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
77 # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
78 # 2 WS compliant with VOS=Range1 and 24 MHz.
79 mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
80 mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
81 # Boost JTAG frequency
85 $_TARGETNAME configure -event reset-start {
86 # Reset clock is MSI (4 MHz)
90 $_TARGETNAME configure -event examine-end {
91 # Enable debug during low power modes (uses more power)
92 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
93 mmw 0xE0042004 0x00000007 0
95 # Stop watchdog counters during halt
96 # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
97 mmw 0xE004203C 0x00001800 0
100 $_TARGETNAME configure -event trace-config {
101 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
102 # change this value accordingly to configure trace pins
104 mmw 0xE0042004 0x00000020 0