1 # STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
2 # http://www.st.com/stm32mp1
4 # HLA does not support multi-cores nor custom CSW nor AP other than 0
6 echo "ERROR: HLA transport cannot work with this target."
7 echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
11 source [find target/swj-dp.tcl]
13 if { [info exists CHIPNAME] } {
14 set _CHIPNAME $CHIPNAME
16 set _CHIPNAME stm32mp15x
19 if { [info exists CPUTAPID] } {
20 set _CPUTAPID $CPUTAPID
23 set _CPUTAPID 0x6ba00477
25 set _CPUTAPID 0x6ba02477
29 # Chip Level TAP Controller, only in jtag mode
30 if { [info exists CLCTAPID] } {
31 set _CLCTAPID $CLCTAPID
33 set _CLCTAPID 0x06500041
36 swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
38 jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
43 # FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
44 # so defer-examine it until the reset framework get merged
45 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
46 # NOTE: do not change the order of target create
47 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
48 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
49 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
50 target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
51 target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
52 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
54 targets $_CHIPNAME.cpu0
56 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
57 $_CHIPNAME.cpu0 cortex_a maskisr on
58 $_CHIPNAME.cpu1 cortex_a maskisr on
59 $_CHIPNAME.cpu0 cortex_a dacrfixup on
60 $_CHIPNAME.cpu1 cortex_a dacrfixup on
62 cti create $_CHIPNAME.cti.sys -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0094000
63 cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D8000
64 cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE00D9000
65 cti create $_CHIPNAME.cti.cm4 -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xE0043000
67 swo create $_CHIPNAME.swo -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0083000
68 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0xE0093000
70 # interface does not work while srst is asserted
71 # this is target specific, valid for every board
72 # Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
73 # srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
74 # debug unit, behavior equivalent to "srst_pulls_trst"
75 reset_config srst_gates_jtag srst_pulls_trst
78 adapter srst pulse_width 200
79 # bootrom has an internal timeout of 1 second for detecting the boot flash.
80 # wait at least 1 second to guarantee we are out of bootrom
81 adapter srst delay 1100
83 add_help_text axi_secure "Set secure mode for following AXI accesses"
85 $::_CHIPNAME.dap apsel 0
86 $::_CHIPNAME.dap apcsw 0x10006000
89 add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
91 $::_CHIPNAME.dap apsel 0
92 $::_CHIPNAME.dap apcsw 0x30006000
97 proc dbgmcu_enable_debug {} {
98 # set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
99 catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
102 proc toggle_cpu0_dbg_claim0 {} {
103 # toggle CPU0 DBG_CLAIM[0]
104 $::_CHIPNAME.ap1 mww 0xe00d0fa0 1
105 $::_CHIPNAME.ap1 mww 0xe00d0fa4 1
108 proc detect_cpu1 {} {
109 $::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
110 set dual_core [expr $cpu1_prsr(0) & 1]
111 if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
114 proc rcc_enable_traceclk {} {
115 $::_CHIPNAME.ap2 mww 0x5000080c 0x301
118 # FIXME: most of handler below will be removed once reset framework get merged
119 $_CHIPNAME.ap1 configure -event reset-deassert-pre {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
120 $_CHIPNAME.ap2 configure -event reset-deassert-pre {dbgmcu_enable_debug;rcc_enable_traceclk}
121 $_CHIPNAME.cpu0 configure -event reset-deassert-pre {$::_CHIPNAME.cpu0 arp_examine}
122 $_CHIPNAME.cpu1 configure -event reset-deassert-pre {$::_CHIPNAME.cpu1 arp_examine allow-defer}
123 $_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
124 $_CHIPNAME.cm4 configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
125 $_CHIPNAME.ap1 configure -event examine-start {dap init}
126 $_CHIPNAME.ap2 configure -event examine-start {dbgmcu_enable_debug}
127 $_CHIPNAME.cpu0 configure -event examine-end {detect_cpu1}
128 $_CHIPNAME.ap2 configure -event examine-end {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}