2 # stm32l1 devices support both JTAG and SWD transports.
5 source [find target/swj-dp.tcl]
6 source [find mem_helper.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
16 # Work-area is a space in RAM used for flash programming
18 if { [info exists WORKAREASIZE] } {
19 set _WORKAREASIZE $WORKAREASIZE
21 set _WORKAREASIZE 0x2800
24 # JTAG speed should be <= F_CPU/6.
25 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
28 adapter_nsrst_delay 100
34 if { [info exists CPUTAPID] } {
35 set _CPUTAPID $CPUTAPID
38 # See STM Document RM0038
39 # Section 30.6.3 - corresponds to Cortex-M3 r2p0
40 set _CPUTAPID 0x4ba00477
42 # SWD IDCODE (single drop, arm)
43 set _CPUTAPID 0x2ba01477
47 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
50 jtag newtap $_CHIPNAME bs -irlen 5
53 set _TARGETNAME $_CHIPNAME.cpu
54 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
56 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
58 # flash size will be probed
59 set _FLASHNAME $_CHIPNAME.flash
60 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
62 reset_config srst_nogate
65 # if srst is not fitted use SYSRESETREQ to
66 # perform a soft reset
67 cortex_m reset_config sysresetreq
70 proc stm32l_enable_HSI {} {
71 # Enable HSI as clock source
72 echo "STM32L: Enabling HSI"
75 mww 0x40023800 0x00000101
78 mww 0x40023808 0x00000001
84 $_TARGETNAME configure -event reset-init {
88 $_TARGETNAME configure -event reset-start {
92 $_TARGETNAME configure -event examine-end {
93 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
94 mmw 0xE0042004 0x00000007 0
96 # Stop watchdog counters during halt
97 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
98 mmw 0xE0042008 0x00001800 0
101 $_TARGETNAME configure -event trace-config {
102 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
103 # change this value accordingly to configure trace pins
105 mmw 0xE0042004 0x00000020 0