2 # M0+ devices only have SW-DP, but swj-dp code works, just don't
3 # set any jtag related features
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
14 # Work-area is a space in RAM used for flash programming
15 # By default use 8kB (max ram on smallest part)
16 if { [info exists WORKAREASIZE] } {
17 set _WORKAREASIZE $WORKAREASIZE
19 set _WORKAREASIZE 0x2000
22 # JTAG speed should be <= F_CPU/6.
23 # F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
26 adapter_nsrst_delay 100
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
31 # Arm, m0+, non-multidrop.
32 # http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
33 set _CPUTAPID 0x0bc11477
36 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
38 set _TARGETNAME $_CHIPNAME.cpu
39 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
41 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
43 # flash size will be probed
44 set _FLASHNAME $_CHIPNAME.flash
45 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
48 # if srst is not fitted use SYSRESETREQ to
49 # perform a soft reset
50 cortex_m reset_config sysresetreq
53 proc stm32l0_enable_HSI16 {} {
54 # Enable HSI16 as clock source
55 echo "STM32L0: Enabling HSI16"
57 # Set HSI16ON in RCC_CR (leave MSI enabled)
58 mww 0x40021000 0x00000101
60 # Set HSI16 as SYSCLK (RCC_CFGR)
61 mww 0x4002100c 0x00000001
67 $_TARGETNAME configure -event reset-init {
71 $_TARGETNAME configure -event reset-start {