1 # script for stm32h7x family
4 # stm32h7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32h7x
15 if { [info exists DUAL_BANK] } {
16 set $_CHIPNAME.DUAL_BANK $DUAL_BANK
19 set $_CHIPNAME.DUAL_BANK 0
22 if { [info exists DUAL_CORE] } {
23 set $_CHIPNAME.DUAL_CORE $DUAL_CORE
26 set $_CHIPNAME.DUAL_CORE 0
29 # Issue a warning when hla is used, and fallback to single core configuration
30 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
31 echo "Warning : hla does not support multicore debugging"
32 set $_CHIPNAME.DUAL_CORE 0
35 if { [info exists USE_CTI] } {
36 set $_CHIPNAME.USE_CTI $USE_CTI
39 set $_CHIPNAME.USE_CTI 0
42 # Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
43 if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
44 echo "Warning : could not use CTI with a single core device, CTI is disabled"
45 set $_CHIPNAME.USE_CTI 0
50 # Work-area is a space in RAM used for flash programming
52 if { [info exists WORKAREASIZE] } {
53 set _WORKAREASIZE $WORKAREASIZE
55 set _WORKAREASIZE 0x10000
59 if { [info exists CPUTAPID] } {
60 set _CPUTAPID $CPUTAPID
63 set _CPUTAPID 0x6ba00477
65 set _CPUTAPID 0x6ba02477
69 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
70 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
73 jtag newtap $_CHIPNAME bs -irlen 5
77 # STM32H7 provides an APB-AP at access port 2, which allows the access to
78 # the debug and trace features on the system APB System Debug Bus (APB-D).
79 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
82 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
84 $_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
86 flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
88 if {[set $_CHIPNAME.DUAL_BANK]} {
89 flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
92 if {[set $_CHIPNAME.DUAL_CORE]} {
93 target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
95 $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
97 flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
99 if {[set $_CHIPNAME.DUAL_BANK]} {
100 flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
104 # Make sure that cpu0 is selected
105 targets $_CHIPNAME.cpu0
107 if { [info exists QUADSPI] && $QUADSPI } {
108 set a [llength [flash list]]
109 set _QSPINAME $_CHIPNAME.qspi
110 flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
112 if { [info exists OCTOSPI1] && $OCTOSPI1 } {
113 set a [llength [flash list]]
114 set _OCTOSPINAME1 $_CHIPNAME.octospi1
115 flash bank $_OCTOSPINAME1 stmqspi 0x90000000 0 0 0 $_CHIPNAME.cpu0 0x52005000
117 if { [info exists OCTOSPI2] && $OCTOSPI2 } {
118 set b [llength [flash list]]
119 set _OCTOSPINAME2 $_CHIPNAME.octospi2
120 flash bank $_OCTOSPINAME2 stmqspi 0x70000000 0 0 0 $_CHIPNAME.cpu0 0x5200A000
124 # Clock after reset is HSI at 64 MHz, no need of PLL
127 adapter srst delay 100
134 # The STM32H7 does not support connect_assert_srst mode because the AXI is
135 # unavailable while SRST is asserted, and that is used to access the DBGMCU
136 # component at 0x5C001000 in the examine-end event handler.
138 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
139 # of the default AP0, and that works with SRST asserted; however, nonzero AP
140 # usage does not work with HLA, so is not done by default. That change could be
141 # made in a local configuration file if connect_assert_srst mode is needed for
142 # a specific application and a non-HLA adapter is in use.
143 reset_config srst_only srst_nogate
146 # if srst is not fitted use SYSRESETREQ to
147 # perform a soft reset
148 $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
150 if {[set $_CHIPNAME.DUAL_CORE]} {
151 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
154 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
155 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
156 # makes the data access cacheable. This allows reading and writing data in the
157 # CPU cache from the debugger, which is far more useful than going straight to
158 # RAM when operating on typical variables, and is generally no worse when
159 # operating on special memory locations.
160 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
163 $_CHIPNAME.cpu0 configure -event examine-end {
164 # Enable D3 and D1 DBG clocks
165 # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
166 stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
168 # Enable debug during low power modes (uses more power)
169 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D1 Domain
170 stm32h7x_dbgmcu_mmw 0x004 0x00000007 0
171 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP D2 Domain
172 stm32h7x_dbgmcu_mmw 0x004 0x00000038 0
174 # Stop watchdog counters during halt
175 # DBGMCU_APB3FZ1 |= WWDG1
176 stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
177 # DBGMCU_APB1LFZ1 |= WWDG2
178 stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
179 # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
180 stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
183 $_CHIPNAME.cpu0 configure -event trace-config {
184 # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
185 # change this value accordingly to configure trace pins
187 stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
190 $_CHIPNAME.cpu0 configure -event reset-init {
191 # Clock after reset is HSI at 64 MHz, no need of PLL
195 # get _CHIPNAME from current target
196 proc stm32h7x_get_chipname {} {
197 set t [target current]
198 set sep [string last "." $t]
202 return [string range $t 0 [expr $sep - 1]]
205 if {[set $_CHIPNAME.DUAL_CORE]} {
206 $_CHIPNAME.cpu1 configure -event examine-end {
207 set _CHIPNAME [stm32h7x_get_chipname]
208 global $_CHIPNAME.USE_CTI
210 # Stop watchdog counters during halt
211 # DBGMCU_APB3FZ2 |= WWDG1
212 stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
213 # DBGMCU_APB1LFZ2 |= WWDG2
214 stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
215 # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
216 stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
218 if {[set $_CHIPNAME.USE_CTI]} {
224 # like mrw, but with target selection
225 proc stm32h7x_mrw {used_target reg} {
227 $used_target mem2array value 32 $reg 1
231 # like mmw, but with target selection
232 proc stm32h7x_mmw {used_target reg setbits clearbits} {
233 set old [stm32h7x_mrw $used_target $reg]
234 set new [expr ($old & ~$clearbits) | $setbits]
235 $used_target mww $reg $new
238 # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
239 # this procedure will use the mem_ap on AP2 whenever possible
240 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
241 # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
243 set _CHIPNAME [stm32h7x_get_chipname]
244 set used_target $_CHIPNAME.ap2
245 set reg_addr [expr 0xE00E1000 + $reg_offset]
247 set used_target [target current]
248 set reg_addr [expr 0x5C001000 + $reg_offset]
251 stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
254 if {[set $_CHIPNAME.USE_CTI]} {
255 # create CTI instances for both cores
256 cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0043000
257 cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xE0043000
259 $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
260 $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
262 $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
263 $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
265 proc stm32h7x_cti_start {} {
266 set _CHIPNAME [stm32h7x_get_chipname]
268 # Configure Cores' CTIs to halt each other
269 # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
270 $_CHIPNAME.cti0 write INEN0 0x1
271 $_CHIPNAME.cti0 write OUTEN0 0x1
272 $_CHIPNAME.cti1 write INEN0 0x1
273 $_CHIPNAME.cti1 write OUTEN0 0x1
276 $_CHIPNAME.cti0 enable on
277 $_CHIPNAME.cti1 enable on
280 proc stm32h7x_cti_stop {} {
281 set _CHIPNAME [stm32h7x_get_chipname]
283 $_CHIPNAME.cti0 enable off
284 $_CHIPNAME.cti1 enable off
287 proc stm32h7x_cti_prepare_restart_all {} {
288 stm32h7x_cti_prepare_restart cti0
289 stm32h7x_cti_prepare_restart cti1
292 proc stm32h7x_cti_prepare_restart {cti} {
293 set _CHIPNAME [stm32h7x_get_chipname]
295 # Acknowlodge EDBGRQ at TRIGOUT0
296 $_CHIPNAME.$cti write INACK 0x01
297 $_CHIPNAME.$cti write INACK 0x00