1 # script for stm32h7x family
4 # stm32h7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32h7x
15 if { [info exists DUAL_BANK] } {
16 set $_CHIPNAME.DUAL_BANK $DUAL_BANK
19 set $_CHIPNAME.DUAL_BANK 0
22 if { [info exists DUAL_CORE] } {
23 set $_CHIPNAME.DUAL_CORE $DUAL_CORE
26 set $_CHIPNAME.DUAL_CORE 0
29 # Issue a warning when hla is used, and fallback to single core configuration
30 if { [set $_CHIPNAME.DUAL_CORE] && [using_hla] } {
31 echo "Warning : hla does not support multicore debugging"
32 set $_CHIPNAME.DUAL_CORE 0
35 if { [info exists USE_CTI] } {
36 set $_CHIPNAME.USE_CTI $USE_CTI
39 set $_CHIPNAME.USE_CTI 0
42 # Issue a warning when DUAL_CORE=0 and USE_CTI=1, and fallback to USE_CTI=0
43 if { ![set $_CHIPNAME.DUAL_CORE] && [set $_CHIPNAME.USE_CTI] } {
44 echo "Warning : could not use CTI with a single core device, CTI is disabled"
45 set $_CHIPNAME.USE_CTI 0
50 # Work-area is a space in RAM used for flash programming
52 if { [info exists WORKAREASIZE] } {
53 set _WORKAREASIZE $WORKAREASIZE
55 set _WORKAREASIZE 0x10000
59 if { [info exists CPUTAPID] } {
60 set _CPUTAPID $CPUTAPID
63 set _CPUTAPID 0x6ba00477
65 set _CPUTAPID 0x6ba02477
69 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
70 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
73 swj_newdap $_CHIPNAME bs -irlen 5
77 # STM32H7 provides an APB-AP at access port 2, which allows the access to
78 # the debug and trace features on the system APB System Debug Bus (APB-D).
79 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
82 target create $_CHIPNAME.cpu0 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 0
84 $_CHIPNAME.cpu0 configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
86 flash bank $_CHIPNAME.bank1.cpu0 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu0
88 if {[set $_CHIPNAME.DUAL_BANK]} {
89 flash bank $_CHIPNAME.bank2.cpu0 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu0
92 if {[set $_CHIPNAME.DUAL_CORE]} {
93 target create $_CHIPNAME.cpu1 cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap -ap-num 3
95 $_CHIPNAME.cpu1 configure -work-area-phys 0x38000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
97 flash bank $_CHIPNAME.bank1.cpu1 stm32h7x 0x08000000 0 0 0 $_CHIPNAME.cpu1
99 if {[set $_CHIPNAME.DUAL_BANK]} {
100 flash bank $_CHIPNAME.bank2.cpu1 stm32h7x 0x08100000 0 0 0 $_CHIPNAME.cpu1
104 # Make sure that cpu0 is selected
105 targets $_CHIPNAME.cpu0
107 # Clock after reset is HSI at 64 MHz, no need of PLL
110 adapter srst delay 100
117 # The STM32H7 does not support connect_assert_srst mode because the AXI is
118 # unavailable while SRST is asserted, and that is used to access the DBGMCU
119 # component at 0x5C001000 in the examine-end event handler.
121 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
122 # of the default AP0, and that works with SRST asserted; however, nonzero AP
123 # usage does not work with HLA, so is not done by default. That change could be
124 # made in a local configuration file if connect_assert_srst mode is needed for
125 # a specific application and a non-HLA adapter is in use.
126 reset_config srst_only srst_nogate
129 # if srst is not fitted use SYSRESETREQ to
130 # perform a soft reset
131 $_CHIPNAME.cpu0 cortex_m reset_config sysresetreq
133 if {[set $_CHIPNAME.DUAL_CORE]} {
134 $_CHIPNAME.cpu1 cortex_m reset_config sysresetreq
137 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
138 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
139 # makes the data access cacheable. This allows reading and writing data in the
140 # CPU cache from the debugger, which is far more useful than going straight to
141 # RAM when operating on typical variables, and is generally no worse when
142 # operating on special memory locations.
143 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
146 $_CHIPNAME.cpu0 configure -event examine-end {
147 # Enable D3 and D1 DBG clocks
148 # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
149 stm32h7x_dbgmcu_mmw 0x004 0x00600000 0
151 # Enable debug during low power modes (uses more power)
152 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3, D2 & D1 Domains
153 stm32h7x_dbgmcu_mmw 0x004 0x000001BF 0
155 # Stop watchdog counters during halt
156 # DBGMCU_APB3FZ1 |= WWDG1
157 stm32h7x_dbgmcu_mmw 0x034 0x00000040 0
158 # DBGMCU_APB1LFZ1 |= WWDG2
159 stm32h7x_dbgmcu_mmw 0x03C 0x00000800 0
160 # DBGMCU_APB4FZ1 |= WDGLSD1 | WDGLSD2
161 stm32h7x_dbgmcu_mmw 0x054 0x000C0000 0
164 $_CHIPNAME.cpu0 configure -event trace-config {
165 # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
166 # change this value accordingly to configure trace pins
168 stm32h7x_dbgmcu_mmw 0x004 0x00100000 0
171 $_CHIPNAME.cpu0 configure -event reset-init {
172 # Clock after reset is HSI at 64 MHz, no need of PLL
176 if {[set $_CHIPNAME.DUAL_CORE]} {
177 $_CHIPNAME.cpu1 configure -event examine-end {
178 # get _CHIPNAME from the current target
179 set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
180 global $_CHIPNAME.USE_CTI
182 # Stop watchdog counters during halt
183 # DBGMCU_APB3FZ2 |= WWDG1
184 stm32h7x_dbgmcu_mmw 0x038 0x00000040 0
185 # DBGMCU_APB1LFZ2 |= WWDG2
186 stm32h7x_dbgmcu_mmw 0x040 0x00000800 0
187 # DBGMCU_APB4FZ2 |= WDGLSD1 | WDGLSD2
188 stm32h7x_dbgmcu_mmw 0x058 0x000C0000 0
190 if {[set $_CHIPNAME.USE_CTI]} {
196 # like mrw, but with target selection
197 proc stm32h7x_mrw {used_target reg} {
199 $used_target mem2array value 32 $reg 1
203 # like mmw, but with target selection
204 proc stm32h7x_mmw {used_target reg setbits clearbits} {
205 set old [stm32h7x_mrw $used_target $reg]
206 set new [expr ($old & ~$clearbits) | $setbits]
207 $used_target mww $reg $new
210 # mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base
211 # this procedure will use the mem_ap on AP2 whenever possible
212 proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {
213 # use $_CHIPNAME.ap2 if possible, and use the proper dbgmcu base address
215 # get _CHIPNAME from the current target
216 set _CHIPNAME [regsub ".(cpu|ap)\\d*$" [target current] ""]
217 set used_target $_CHIPNAME.ap2
218 set reg_addr [expr 0xE00E1000 + $reg_offset]
220 set used_target [target current]
221 set reg_addr [expr 0x5C001000 + $reg_offset]
224 stm32h7x_mmw $used_target $reg_addr $setbits $clearbits
227 if {[set $_CHIPNAME.USE_CTI]} {
228 # create CTI instances for both cores
229 cti create $_CHIPNAME.cti0 -dap $_CHIPNAME.dap -ap-num 0 -ctibase 0xE0043000
230 cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 3 -ctibase 0xE0043000
232 $_CHIPNAME.cpu0 configure -event halted { stm32h7x_cti_prepare_restart_all }
233 $_CHIPNAME.cpu1 configure -event halted { stm32h7x_cti_prepare_restart_all }
235 $_CHIPNAME.cpu0 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
236 $_CHIPNAME.cpu1 configure -event debug-halted { stm32h7x_cti_prepare_restart_all }
238 proc stm32h7x_cti_start {} {
239 # get _CHIPNAME from the current target
240 set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
242 # Configure Cores' CTIs to halt each other
243 # TRIGIN0 (DBGTRIGGER) and TRIGOUT0 (EDBGRQ) at CTM_CHANNEL_0
244 $_CHIPNAME.cti0 write INEN0 0x1
245 $_CHIPNAME.cti0 write OUTEN0 0x1
246 $_CHIPNAME.cti1 write INEN0 0x1
247 $_CHIPNAME.cti1 write OUTEN0 0x1
250 $_CHIPNAME.cti0 enable on
251 $_CHIPNAME.cti1 enable on
254 proc stm32h7x_cti_stop {} {
255 # get _CHIPNAME from the current target
256 set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
258 $_CHIPNAME.cti0 enable off
259 $_CHIPNAME.cti1 enable off
262 proc stm32h7x_cti_prepare_restart_all {} {
263 stm32h7x_cti_prepare_restart cti0
264 stm32h7x_cti_prepare_restart cti1
267 proc stm32h7x_cti_prepare_restart {cti} {
268 # get _CHIPNAME from the current target
269 set _CHIPNAME [regsub ".cpu\\d$" [target current] ""]
271 # Acknowlodge EDBGRQ at TRIGOUT0
272 $_CHIPNAME.$cti write INACK 0x01
273 $_CHIPNAME.$cti write INACK 0x00