1 # script for stm32h7x family
4 # stm32h7 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32h7x
17 # Work-area is a space in RAM used for flash programming
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x10000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 set _CPUTAPID 0x6ba00477
32 set _CPUTAPID 0x6ba02477
36 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
37 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
40 swj_newdap $_CHIPNAME bs -irlen 5
43 set _TARGETNAME $_CHIPNAME.cpu
44 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
46 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
48 set _FLASHNAME $_CHIPNAME.flash
49 flash bank $_FLASHNAME stm32h7x 0x08000000 0 0 0 $_TARGETNAME
51 # Clock after reset is HSI at 64 MHz, no need of PLL
54 adapter_nsrst_delay 100
61 # The STM32H7 does not support connect_assert_srst mode because the AXI is
62 # unavailable while SRST is asserted, and that is used to access the DBGMCU
63 # component at 0x5C001000 in the examine-end event handler.
65 # It is possible to access the DBGMCU component at 0xE00E1000 via AP2 instead
66 # of the default AP0, and that works with SRST asserted; however, nonzero AP
67 # usage does not work with HLA, so is not done by default. That change could be
68 # made in a local configuration file if connect_assert_srst mode is needed for
69 # a specific application and a non-HLA adapter is in use.
70 reset_config srst_only srst_nogate
73 # if srst is not fitted use SYSRESETREQ to
74 # perform a soft reset
75 cortex_m reset_config sysresetreq
77 # Set CSW[27], which according to ARM ADI v5 appendix E1.4 maps to AHB signal
78 # HPROT[3], which according to AMBA AHB/ASB/APB specification chapter 3.7.3
79 # makes the data access cacheable. This allows reading and writing data in the
80 # CPU cache from the debugger, which is far more useful than going straight to
81 # RAM when operating on typical variables, and is generally no worse when
82 # operating on special memory locations.
83 $_CHIPNAME.dap apcsw 0x08000000 0x08000000
86 $_TARGETNAME configure -event examine-end {
87 # Enable D3 and D1 DBG clocks
88 # DBGMCU_CR |= D3DBGCKEN | D1DBGCKEN
89 mmw 0x5C001004 0x00600000 0
91 # Enable debug during low power modes (uses more power)
92 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP in D3 & D1 Domains
93 mmw 0x5C001004 0x00000187 0
95 # Stop watchdog counters during halt
96 # DBGMCU_APB3FZ1 |= WWDG1
97 mmw 0x5C001034 0x00000040 0
98 # DBGMCU_APB4FZ1 |= WDGLSD1
99 mmw 0x5C001054 0x00040000 0
102 $_TARGETNAME configure -event trace-config {
103 # Set TRACECLKEN; TRACE_MODE is set to async; when using sync
104 # change this value accordingly to configure trace pins
106 mmw 0x5C001004 0x00100000 0
109 $_TARGETNAME configure -event reset-init {
110 # Clock after reset is HSI at 64 MHz, no need of PLL