1 # script for stm32f4x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
8 if { [info exists CHIPNAME] } {
9 set _CHIPNAME $CHIPNAME
11 set _CHIPNAME stm32f4x
16 # Work-area is a space in RAM used for flash programming
18 if { [info exists WORKAREASIZE] } {
19 set _WORKAREASIZE $WORKAREASIZE
21 set _WORKAREASIZE 0x10000
25 if { [info exists CPUTAPID] } {
26 set _CPUTAPID $CPUTAPID
29 # See STM Document RM0090
30 # Section 38.6.3 - corresponds to Cortex-M4 r0p1
31 set _CPUTAPID 0x4ba00477
33 set _CPUTAPID 0x2ba01477
37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 if { [info exists BSTAPID] } {
42 # See STM Document RM0090
44 # STM32F405xx/07xx and STM32F415xx/17xx
45 set _BSTAPID1 0x06413041
46 # STM32F42xxx and STM32F43xxx
47 set _BSTAPID2 0x06419041
48 # See STM Document RM0368 (Rev. 3)
50 set _BSTAPID3 0x06423041
52 set _BSTAPID4 0x06433041
53 # See STM Document RM0383 (Rev 2)
55 set _BSTAPID5 0x06431041
59 swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
60 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
61 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
64 set _TARGETNAME $_CHIPNAME.cpu
65 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
67 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
69 set _FLASHNAME $_CHIPNAME.flash
70 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
72 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
74 # Since we may be running of an RC oscilator, we crank down the speed a
75 # bit more to be on the safe side. Perhaps superstition, but if are
76 # running off a crystal, we can run closer to the limit. Note
77 # that there can be a pretty wide band where things are more or less stable.
80 adapter_nsrst_delay 100
85 reset_config srst_nogate
88 # if srst is not fitted use SYSRESETREQ to
89 # perform a soft reset
90 cortex_m reset_config sysresetreq