1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32f4x family
6 # stm32f4 devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32f4x
19 # Work-area is a space in RAM used for flash programming
20 # By default use 32kB (Available RAM in smallest device STM32F410)
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x8000
28 if { [info exists CPUTAPID] } {
29 set _CPUTAPID $CPUTAPID
32 # See STM Document RM0090
33 # Section 38.6.3 - corresponds to Cortex-M4 r0p1
34 set _CPUTAPID 0x4ba00477
36 set _CPUTAPID 0x2ba01477
40 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
41 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
43 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
46 jtag newtap $_CHIPNAME bs -irlen 5
49 set _TARGETNAME $_CHIPNAME.cpu
50 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
52 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
54 set _FLASHNAME $_CHIPNAME.flash
55 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
57 flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
59 if { [info exists QUADSPI] && $QUADSPI } {
60 set a [llength [flash list]]
61 set _QSPINAME $_CHIPNAME.qspi
62 flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
65 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
67 # Since we may be running of an RC oscilator, we crank down the speed a
68 # bit more to be on the safe side. Perhaps superstition, but if are
69 # running off a crystal, we can run closer to the limit. Note
70 # that there can be a pretty wide band where things are more or less stable.
73 adapter srst delay 100
78 reset_config srst_nogate
81 # if srst is not fitted use SYSRESETREQ to
82 # perform a soft reset
83 cortex_m reset_config sysresetreq
86 $_TARGETNAME configure -event examine-end {
87 # Enable debug during low power modes (uses more power)
88 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
89 mmw 0xE0042004 0x00000007 0
91 # Stop watchdog counters during halt
92 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
93 mmw 0xE0042008 0x00001800 0
96 proc proc_post_enable {_chipname} {
97 targets $_chipname.cpu
99 if { [$_chipname.tpiu cget -protocol] eq "sync" } {
100 switch [$_chipname.tpiu cget -port-width] {
102 mmw 0xE0042004 0x00000060 0x000000c0
103 mmw 0x40021020 0x00000000 0x0000ff00
104 mmw 0x40021000 0x000000a0 0x000000f0
105 mmw 0x40021008 0x000000f0 0x00000000
108 mmw 0xE0042004 0x000000a0 0x000000c0
109 mmw 0x40021020 0x00000000 0x000fff00
110 mmw 0x40021000 0x000002a0 0x000003f0
111 mmw 0x40021008 0x000003f0 0x00000000
114 mmw 0xE0042004 0x000000e0 0x000000c0
115 mmw 0x40021020 0x00000000 0x0fffff00
116 mmw 0x40021000 0x00002aa0 0x00003ff0
117 mmw 0x40021008 0x00003ff0 0x00000000
121 mmw 0xE0042004 0x00000020 0x000000c0
125 $_CHIPNAME.tpiu configure -event post-enable "proc_post_enable $_CHIPNAME"
127 $_TARGETNAME configure -event reset-init {
128 # Configure PLL to boost clock to HSI x 4 (64 MHz)
129 mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
130 mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
131 mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
132 sleep 10 ;# Wait for PLL to lock
133 mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
134 mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
136 # Boost JTAG frequency
140 $_TARGETNAME configure -event reset-start {
141 # Reduce speed since CPU speed will slow down to 16MHz with the reset