1 # script for stm32f4x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f4x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 32kB (Available RAM in smallest device STM32F410)
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x8000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0090
31 # Section 38.6.3 - corresponds to Cortex-M4 r0p1
32 set _CPUTAPID 0x4ba00477
34 set _CPUTAPID 0x2ba01477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
40 if { [info exists BSTAPID] } {
43 # See STM Document RM0090
45 # STM32F405xx/07xx and STM32F415xx/17xx
46 set _BSTAPID1 0x06413041
47 # STM32F42xxx and STM32F43xxx
48 set _BSTAPID2 0x06419041
49 # See STM Document RM0368 (Rev. 3)
51 set _BSTAPID3 0x06423041
53 set _BSTAPID4 0x06433041
54 # See STM Document RM0383 (Rev 2)
56 set _BSTAPID5 0x06431041
57 # See STM Document RM0386
59 set _BSTAPID6 0x06434041
60 # See STM Document RM0401
62 set _BSTAPID7 0x06458041
64 set _BSTAPID8 0x06441041
68 swj_newdap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \
69 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 \
70 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5 \
71 -expected-id $_BSTAPID6 -expected-id $_BSTAPID7 \
72 -expected-id $_BSTAPID8
75 set _TARGETNAME $_CHIPNAME.cpu
76 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
78 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
80 set _FLASHNAME $_CHIPNAME.flash
81 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
83 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
85 # Since we may be running of an RC oscilator, we crank down the speed a
86 # bit more to be on the safe side. Perhaps superstition, but if are
87 # running off a crystal, we can run closer to the limit. Note
88 # that there can be a pretty wide band where things are more or less stable.
91 adapter_nsrst_delay 100
96 reset_config srst_nogate
99 # if srst is not fitted use SYSRESETREQ to
100 # perform a soft reset
101 cortex_m reset_config sysresetreq
104 $_TARGETNAME configure -event examine-end {
105 # Enable debug during low power modes (uses more power)
106 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
107 mmw 0xE0042004 0x00000007 0
109 # Stop watchdog counters during halt
110 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
111 mmw 0xE0042008 0x00001800 0
114 $_TARGETNAME configure -event trace-config {
115 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
116 # change this value accordingly to configure trace pins
118 mmw 0xE0042004 0x00000020 0
121 $_TARGETNAME configure -event reset-init {
122 # Configure PLL to boost clock to HSI x 4 (64 MHz)
123 mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
124 mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
125 mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
126 sleep 10 ;# Wait for PLL to lock
127 mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
128 mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
130 # Boost JTAG frequency
134 $_TARGETNAME configure -event reset-start {
135 # Reduce speed since CPU speed will slow down to 16MHz with the reset