1 # script for stm32f4x family
4 # stm32 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32f4x
17 # Work-area is a space in RAM used for flash programming
18 # By default use 32kB (Available RAM in smallest device STM32F410)
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x8000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0090
31 # Section 38.6.3 - corresponds to Cortex-M4 r0p1
32 set _CPUTAPID 0x4ba00477
34 set _CPUTAPID 0x2ba01477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
39 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
42 jtag newtap $_CHIPNAME bs -irlen 5
45 set _TARGETNAME $_CHIPNAME.cpu
46 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
48 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
50 set _FLASHNAME $_CHIPNAME.flash
51 flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
53 flash bank $_CHIPNAME.otp stm32f2x 0x1fff7800 0 0 0 $_TARGETNAME
55 if { [info exists QUADSPI] && $QUADSPI } {
56 set a [llength [flash list]]
57 set _QSPINAME $_CHIPNAME.qspi
58 flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
61 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 16MHz, so use F_JTAG = 2MHz
63 # Since we may be running of an RC oscilator, we crank down the speed a
64 # bit more to be on the safe side. Perhaps superstition, but if are
65 # running off a crystal, we can run closer to the limit. Note
66 # that there can be a pretty wide band where things are more or less stable.
69 adapter srst delay 100
74 reset_config srst_nogate
77 # if srst is not fitted use SYSRESETREQ to
78 # perform a soft reset
79 cortex_m reset_config sysresetreq
82 $_TARGETNAME configure -event examine-end {
83 # Enable debug during low power modes (uses more power)
84 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
85 mmw 0xE0042004 0x00000007 0
87 # Stop watchdog counters during halt
88 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
89 mmw 0xE0042008 0x00001800 0
92 $_TARGETNAME configure -event trace-config {
93 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
94 # change this value accordingly to configure trace pins
96 mmw 0xE0042004 0x00000020 0
99 $_TARGETNAME configure -event reset-init {
100 # Configure PLL to boost clock to HSI x 4 (64 MHz)
101 mww 0x40023804 0x08012008 ;# RCC_PLLCFGR 16 Mhz /8 (M) * 128 (N) /4(P)
102 mww 0x40023C00 0x00000102 ;# FLASH_ACR = PRFTBE | 2(Latency)
103 mmw 0x40023800 0x01000000 0 ;# RCC_CR |= PLLON
104 sleep 10 ;# Wait for PLL to lock
105 mmw 0x40023808 0x00001000 0 ;# RCC_CFGR |= RCC_CFGR_PPRE1_DIV2
106 mmw 0x40023808 0x00000002 0 ;# RCC_CFGR |= RCC_CFGR_SW_PLL
108 # Boost JTAG frequency
112 $_TARGETNAME configure -event reset-start {
113 # Reduce speed since CPU speed will slow down to 16MHz with the reset