1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # script for stm32f1x family
6 # stm32 devices support both JTAG and SWD transports.
8 source [find target/swj-dp.tcl]
9 source [find mem_helper.tcl]
11 if { [info exists CHIPNAME] } {
12 set _CHIPNAME $CHIPNAME
14 set _CHIPNAME stm32f1x
19 # Work-area is a space in RAM used for flash programming
20 # By default use 4kB (as found on some STM32F100s)
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x1000
27 # Allow overriding the Flash bank size
28 if { [info exists FLASH_SIZE] } {
29 set _FLASH_SIZE $FLASH_SIZE
36 if { [info exists CPUTAPID] } {
37 set _CPUTAPID $CPUTAPID
40 # See STM Document RM0008 Section 26.6.3
41 set _CPUTAPID 0x3ba00477
43 # this is the SW-DP tap id not the jtag tap id
44 set _CPUTAPID 0x1ba01477
48 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
49 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
52 jtag newtap $_CHIPNAME bs -irlen 5
55 set _TARGETNAME $_CHIPNAME.cpu
56 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
58 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
60 # flash size will be probed
61 set _FLASHNAME $_CHIPNAME.flash
62 flash bank $_FLASHNAME stm32f1x 0x08000000 $_FLASH_SIZE 0 0 $_TARGETNAME
64 # JTAG speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz
67 adapter srst delay 100
72 reset_config srst_nogate
75 # if srst is not fitted use SYSRESETREQ to
76 # perform a soft reset
77 cortex_m reset_config sysresetreq
80 $_TARGETNAME configure -event examine-end {
81 # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP |
82 # DBG_STANDBY | DBG_STOP | DBG_SLEEP
83 mmw 0xE0042004 0x00000307 0
86 $_TARGETNAME configure -event trace-config {
87 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
88 # change this value accordingly to configure trace pins
90 mmw 0xE0042004 0x00000020 0