1 # TI/Luminary Stellaris LM3S chip family
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
10 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
11 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
12 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
13 # ... we'll ignore the JTAG version field, rather than list every
14 # chip revision that turns up.
15 if { [info exists CPUTAPID ] } {
16 set _CPUTAPID $CPUTAPID
18 set _CPUTAPID 0x0ba00477
21 if { [info exists WORKAREASIZE ] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x2000
27 jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
28 -expected-id $_CPUTAPID -ignore-version
30 # The "lm3s" variant uses a software reset rather than SRST.
31 # This stops the debug registers from being cleared; it works
32 # around an erratum which should be fixed in later silicon.
33 set _TARGETNAME $_CHIPNAME.cpu
34 target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
37 # 8K working area at base of ram, not backed up
39 # NOTE: you may need or want to reconfigure the work area;
40 # some parts have just 6K, and you may want to use other
41 # addresses (at end of mem not beginning) or back it up.
42 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
44 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
45 # LM3S parts don't support RTCK
47 # NOTE: this may be increased by a reset-init handler, after it
48 # configures and enables the PLL. Or you might need to decrease
49 # this, if you're using a slower clock.
51 $_TARGETNAME configure -event reset-start {adapter_khz 500}
53 # flash configuration ... autodetects sizes, autoprobed
54 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME