1 # TI/Luminary Stellaris LM3S chip family
3 # Some devices have errata in returning their device class.
4 # DEVICECLASS is provided as a manual override
5 # Manual setting of a device class of 0xff is not allowed
9 if { [info exists DEVICECLASS] } {
10 set _DEVICECLASS $DEVICECLASS
15 # Luminary chips support both JTAG and SWD transports.
16 # Adapt based on what transport is active.
17 source [find target/swj-dp.tcl]
19 # For now we ignore the SPI and UART options, which
20 # are usable only for ISP style initial flash programming.
22 if { [info exists CHIPNAME] } {
23 set _CHIPNAME $CHIPNAME
28 # CPU TAP ID 0x1ba00477 for early Sandstorm parts
29 # CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
30 # CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
31 # CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest, Firestorm)
32 # CPU TAP ID 0x4ba00477 for Cortex-M4 r0p1 (on Blizzard)
33 # ... we'll ignore the JTAG version field, rather than list every
34 # chip revision that turns up.
35 if { [info exists CPUTAPID] } {
36 set _CPUTAPID $CPUTAPID
38 set _CPUTAPID 0x0ba00477
41 # SWD DAP, and JTAG TAP, take same params for now;
42 # ... even though SWD ignores all except TAPID, and
43 # JTAG shouldn't need anything more then irlen. (and TAPID).
44 swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
45 -expected-id $_CPUTAPID -ignore-version
46 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
48 if { [info exists WORKAREASIZE] } {
49 set _WORKAREASIZE $WORKAREASIZE
51 # default to 2K working area
52 set _WORKAREASIZE 0x800
55 set _TARGETNAME $_CHIPNAME.cpu
56 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
58 # 8K working area at base of ram, not backed up
60 # NOTE: you may need or want to reconfigure the work area;
61 # some parts have just 6K, and you may want to use other
62 # addresses (at end of mem not beginning) or back it up.
63 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
65 # JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
66 # LM3S parts don't support RTCK
68 # NOTE: this may be increased by a reset-init handler, after it
69 # configures and enables the PLL. Or you might need to decrease
70 # this, if you're using a slower clock.
73 source [find mem_helper.tcl]
75 proc reset_peripherals {family} {
77 source [find chip/ti/lm3s/lm3s.tcl]
79 echo "Resetting Core Peripherals"
81 # Disable the PLL and the system clock divider (nop if disabled)
82 mmw $SYSCTL_RCC 0 $SYSCTL_RCC_USESYSDIV
83 mmw $SYSCTL_RCC2 $SYSCTL_RCC2_BYPASS2 0
85 # RCC and RCC2 to their reset values
86 mww $SYSCTL_RCC [expr (0x078e3ad0 | ([mrw $SYSCTL_RCC] & $SYSCTL_RCC_MOSCDIS))]
87 mww $SYSCTL_RCC2 0x07806810
88 mww $SYSCTL_RCC 0x078e3ad1
90 # Reset the deep sleep clock configuration register
91 mww $SYSCTL_DSLPCLKCFG 0x07800000
93 # Reset the clock gating registers
94 mww $SYSCTL_RCGC0 0x00000040
97 mww $SYSCTL_SCGC0 0x00000040
100 mww $SYSCTL_DCGC0 0x00000040
104 # Reset the remaining SysCtl registers
105 mww $SYSCTL_PBORCTL 0
107 mww $SYSCTL_GPIOHBCTL 0
108 mww $SYSCTL_MOSCCTL 0
109 mww $SYSCTL_PIOSCCAL 0
110 mww $SYSCTL_I2SMCLKCFG 0
112 # Reset the peripherals
113 mww $SYSCTL_SRCR0 0xffffffff
114 mww $SYSCTL_SRCR1 0xffffffff
115 mww $SYSCTL_SRCR2 0xffffffff
120 # Clear any pending SysCtl interrupts
121 mww $SYSCTL_MISC 0xffffffff
123 # Wait for any pending flash operations to complete
124 while {[expr [mrw $FLASH_FMC] & 0xffff] != 0} { sleep 1 }
125 while {[expr [mrw $FLASH_FMC2] & 0xffff] != 0} { sleep 1 }
127 # Reset the flash controller registers
130 mww $FLASH_FCMISC 0xffffffff
134 $_TARGETNAME configure -event reset-start {
138 # When nRST is asserted on most Stellaris devices, it clears some of
139 # the debug state. The ARMv7M and Cortex-M3 TRMs say that's wrong;
140 # and OpenOCD depends on those TRMs. So we won't use SRST on those
141 # chips. (Only power-on reset should affect debug state, beyond a
142 # few specified bits; not the chip's nRST input, wired to SRST.)
144 # REVISIT current errata specs don't seem to cover this issue.
145 # Do we have more details than this email?
146 # https://lists.berlios.de/pipermail
147 # /openocd-development/2008-August/003065.html
152 if {$_DEVICECLASS != 0xff} {
153 set device_class $_DEVICECLASS
155 set device_class [expr (([mrw 0x400fe000] >> 16) & 0xff)]
158 if {$device_class == 0 || $device_class == 1 ||
159 $device_class == 3 || $device_class == 5 || $device_class == 0xa} {
161 # Sandstorm, Fury, DustDevil, Blizzard and Snowflake are able to use NVIC SYSRESETREQ
162 cortex_m reset_config sysresetreq
166 # Tempest and Firestorm default to using NVIC VECTRESET
167 # peripherals will need resetting manually, see proc reset_peripherals
168 cortex_m reset_config vectreset
170 # reset peripherals, based on code in
171 # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf
172 reset_peripherals $device_class
176 # flash configuration ... autodetects sizes, autoprobed
177 flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME