1 # SPDX-License-Identifier: GPL-2.0-or-later
4 # - There are a combination of Cortex-A57s, Cortex-A53s, Cortex-A55, Cortex-R7
5 # and Cortex-M33 for each SOC
6 # - Each SOC can boot through the Cortex-A5x cores
8 # Supported RZ/G2 SOCs and their cores:
9 # RZ/G2H: Cortex-A57 x4, Cortex-A53 x4, Cortex-R7
10 # RZ/G2M: Cortex-A57 x2, Cortex-A53 x4, Cortex-R7
11 # RZ/G2N: Cortex-A57 x2, Cortex-R7
12 # RZ/G2E: Cortex-A53 x2, Cortex-R7
13 # RZ/G2L: Cortex-A55 x2, Cortex-M33
16 # There are 2 configuration options:
17 # SOC: Selects the supported SOC. (Default 'G2L')
18 # BOOT_CORE: Selects the booting core. 'CA57', 'CA53' or 'CA55'
21 reset_config trst_and_srst srst_gates_jtag
23 adapter srst delay 500
25 if { [info exists SOC] } {
37 # Set configuration for each SOC and the default 'BOOT_CORE'
40 set _CHIPNAME r8a774ex
48 set _CHIPNAME r8a774ax
56 set _CHIPNAME r8a774bx
64 set _CHIPNAME r8a774c0
72 set _CHIPNAME r9a07g044l
79 error "'$_soc' is invalid!"
83 # If configured, override the default 'CHIPNAME'
84 if { [info exists CHIPNAME] } {
85 set _CHIPNAME $CHIPNAME
88 # If configured, override the default 'BOOT_CORE'
89 if { [info exists BOOT_CORE] } {
90 set _boot_core $BOOT_CORE
93 if { [info exists DAP_TAPID] } {
94 set _DAP_TAPID $DAP_TAPID
96 set _DAP_TAPID 0x6ba00477
99 echo "\t$_soc - $_num_ca57 CA57(s), $_num_ca55 CA55(s), $_num_ca53 CA53(s), $_num_cr7 CR7(s), \
101 echo "\tBoot Core - $_boot_core\n"
103 set _DAPNAME $_CHIPNAME.dap
107 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID \
109 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
110 echo "$_CHIPNAME.cpu"
112 set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
113 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
114 set CA55_DBGBASE {0x10E10000 0x10F10000}
115 set CA55_CTIBASE {0x10E20000 0x10F20000}
116 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
117 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
118 set CR7_DBGBASE 0x80910000
119 set CR7_CTIBASE 0x80918000
120 set CM33_DBGBASE 0xE000E000
121 set CM33_CTIBASE 0xE0042000
125 proc setup_a5x {core_name dbgbase ctibase num boot} {
126 for { set _core 0 } { $_core < $num } { incr _core } {
127 set _TARGETNAME $::_CHIPNAME.$core_name.$_core
128 set _CTINAME $_TARGETNAME.cti
129 cti create $_CTINAME -dap $::_DAPNAME -ap-num $::_ap_num \
130 -baseaddr [lindex $ctibase $_core]
131 target create $_TARGETNAME aarch64 -dap $::_DAPNAME \
132 -ap-num $::_ap_num -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME
133 if { $_core > 0 || $boot == 0 } {
134 $_TARGETNAME configure -defer-examine
136 set ::smp_targets "$::smp_targets $_TARGETNAME"
140 proc setup_cr7 {dbgbase ctibase} {
141 set _TARGETNAME $::_CHIPNAME.r7
142 set _CTINAME $_TARGETNAME.cti
143 cti create $_CTINAME -dap $::_DAPNAME -ap-num 1 -baseaddr $ctibase
144 target create $_TARGETNAME cortex_r4 -dap $::_DAPNAME \
145 -ap-num 1 -dbgbase $dbgbase -defer-examine
148 proc setup_cm33 {dbgbase ctibase} {
149 set _TARGETNAME $::_CHIPNAME.m33
150 set _CTINAME $_TARGETNAME.cti
151 cti create $_CTINAME -dap $::_DAPNAME -ap-num 2 -baseaddr $ctibase
152 target create $_TARGETNAME cortex_m -dap $::_DAPNAME \
153 -ap-num 2 -dbgbase $dbgbase -defer-examine
156 # Organize target list based on the boot core
157 if { $_boot_core == "CA57" } {
158 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
159 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
160 setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
161 } elseif { $_boot_core == "CA53" } {
162 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
163 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
164 setup_cr7 $CR7_DBGBASE $CR7_CTIBASE
165 } elseif { $_boot_core == "CA55" } {
166 setup_a5x a55 $CA55_DBGBASE $CA55_CTIBASE $_num_ca55 1
167 setup_cm33 $CM33_DBGBASE $CM33_CTIBASE
169 echo "SMP targets:$smp_targets"
170 eval "target smp $smp_targets"
172 if { $_soc == "G2L"} {
173 target create $_CHIPNAME.axi_ap mem_ap -dap $_DAPNAME -ap-num 1
176 proc init_reset {mode} {
177 # Assert both resets: equivalent to a power-on reset
178 adapter assert trst assert srst
180 # Deassert TRST to begin TAP communication
181 adapter deassert trst assert srst
183 # TAP should now be responsive, validate the scan-chain