1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # Renesas R-Car Generation 3 SOCs
4 # - There are a combination of Cortex-A57s, Cortex-A53s, and Cortex-R7 for each Gen3 SOC
5 # - Each SOC can boot through any of the, up to 3, core types that it has
6 # e.g. H3 can boot through Cortex-A57, Cortex-A53, or Cortex-R7
8 # Supported Gen3 SOCs and their cores:
9 # H3: Cortex-A57 x 4, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
10 # M3W: Cortex-A57 x 2, Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
11 # M3N: Cortex-A57 x 2, Cortex-R7 x 2 (Lock-Step)
12 # V3U: Cortex-A76 x 8, Cortex-R52 x2 (Lock-Step)
13 # V3H: Cortex-A53 x 4, Cortex-R7 x 2 (Lock-Step)
14 # V3M: Cortex-A53 x 2, Cortex-R7 x 2 (Lock-Step)
15 # E3: Cortex-A53 x 1, Cortex-R7 x 2 (Lock-Step)
19 # There are 2 configuration options:
20 # SOC: Selects the supported SOC. (Default 'H3')
21 # BOOT_CORE: Selects the booting core. 'CA57', 'CA53', or 'CR7'
22 # Defaults to 'CA57' if the SOC has one, else defaults to 'CA53'
24 if { [info exists SOC] } {
36 # Set configuration for each SOC and the default 'BOOT_CORE'
39 set _CHIPNAME r8a77950
46 set _CHIPNAME r8a77960
53 set _CHIPNAME r8a77965
60 set _CHIPNAME r8a77970
67 set _CHIPNAME r8a77980
74 set _CHIPNAME r8a77990
81 set _CHIPNAME r8a77995
88 set _CHIPNAME r8a779a0
94 error "'$_soc' is invalid!"
98 # If configured, override the default 'CHIPNAME'
99 if { [info exists CHIPNAME] } {
100 set _CHIPNAME $CHIPNAME
103 # If configured, override the default 'BOOT_CORE'
104 if { [info exists BOOT_CORE] } {
105 set _boot_core $BOOT_CORE
108 if { [info exists DAP_TAPID] } {
109 set _DAP_TAPID $DAP_TAPID
111 set _DAP_TAPID 0x5ba00477
114 echo "\t$_soc - $_num_ca76 CA76(s), $_num_ca57 CA57(s), $_num_ca53 CA53(s), $_num_cr52 CR52(s), $_num_cr7 CR7(s)"
115 echo "\tBoot Core - $_boot_core\n"
117 set _DAPNAME $_CHIPNAME.dap
120 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
121 dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
123 set CA76_DBGBASE {0x81410000 0x81510000 0x81610000 0x81710000 0x81c10000 0x81d10000 0x81e10000 0x81f10000}
124 set CA76_CTIBASE {0x81420000 0x81520000 0x81620000 0x81720000 0x81c20000 0x81d20000 0x81e20000 0x81f20000}
125 set CA57_DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
126 set CA57_CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
127 set CA53_DBGBASE {0x80C10000 0x80D10000 0x80E10000 0x80F10000}
128 set CA53_CTIBASE {0x80C20000 0x80D20000 0x80E20000 0x80F20000}
129 set CR52_DBGBASE 0x80c10000
130 set CR52_CTIBASE 0x80c20000
131 set CR7_DBGBASE 0x80910000
132 set CR7_CTIBASE 0x80918000
137 proc setup_a5x {core_name dbgbase ctibase num boot} {
142 for { set _core 0 } { $_core < $num } { incr _core } {
143 set _TARGETNAME $_CHIPNAME.$core_name.$_core
144 set _CTINAME $_TARGETNAME.cti
145 cti create $_CTINAME -dap $_DAPNAME -ap-num 1 \
146 -baseaddr [lindex $ctibase $_core]
147 set _command "target create $_TARGETNAME aarch64 -dap $_DAPNAME \
148 -ap-num 1 -dbgbase [lindex $dbgbase $_core] -cti $_CTINAME"
149 if { $_core == 0 && $boot == 1 } {
150 set _targets "$_TARGETNAME"
152 set _command "$_command -defer-examine"
154 set smp_targets "$smp_targets $_TARGETNAME"
159 proc setup_cr7 {core_name dbgbase ctibase num boot} {
162 for { set _core 0 } { $_core < $num } { incr _core } {
163 set _TARGETNAME $_CHIPNAME.$core_name
164 set _CTINAME $_TARGETNAME.cti
165 cti create $_CTINAME -dap $_DAPNAME -ap-num 1 -baseaddr $ctibase
166 set _command "target create $_TARGETNAME cortex_r4 -dap $_DAPNAME \
167 -ap-num 1 -dbgbase $dbgbase"
169 set _targets "$_TARGETNAME"
171 set _command "$_command -defer-examine"
177 # Organize target list based on the boot core
178 if { [string equal $_boot_core CA76] } {
179 setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 1
180 setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 0
181 } elseif { [string equal $_boot_core CA57] } {
182 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 1
183 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
184 setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0
185 } elseif { [string equal $_boot_core CA53] } {
186 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 1
187 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
188 setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 0
189 } elseif { [string equal $_boot_core CR52] } {
190 setup_cr7 r52 $CR52_DBGBASE $CR52_CTIBASE $_num_cr52 1
191 setup_a5x a76 $CA76_DBGBASE $CA76_CTIBASE $_num_ca76 0
193 setup_cr7 r7 $CR7_DBGBASE $CR7_CTIBASE $_num_cr7 1
194 setup_a5x a57 $CA57_DBGBASE $CA57_CTIBASE $_num_ca57 0
195 setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
198 source [find target/renesas_rcar_reset_common.cfg]
200 eval "target smp $smp_targets"